diff options
| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-03 16:08:04 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-03 16:08:04 -0800 |
| commit | eb6c880ddcb06cb011ebd4557d9057d04ab9b4fb (patch) | |
| tree | f53fd2d9108872af5b5166fb9e211c3ef53a5e25 /src/target/arm_dpm.h | |
| parent | adbf40a04537acba3cf5fea7b71dab6ac3249646 (diff) | |
| download | riscv-openocd-eb6c880ddcb06cb011ebd4557d9057d04ab9b4fb.zip riscv-openocd-eb6c880ddcb06cb011ebd4557d9057d04ab9b4fb.tar.gz riscv-openocd-eb6c880ddcb06cb011ebd4557d9057d04ab9b4fb.tar.bz2 | |
ARM DPM: make DSCR bit defs sharable
Move the symbols for these bits from "armv7a.h" to "arm_dpm.h",
where they can be seen and used not just by Cortex-A but also
by the ARM11 (armv6) code.
Change them from bit numbers to bit masks ... this matches the
usage in ARM11 code, and also makes it easier to read.
Rename DSCR_EXT_INT_EN as DSCR_ITR_EN to match the docs; it's
enabling ITR functionality, not external interrupts, so this
changes the name to be less misleading. (There *IS* a bit
affecting interrupts, and this isn't it.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/arm_dpm.h')
| -rw-r--r-- | src/target/arm_dpm.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h index c284144..1f32e8b 100644 --- a/src/target/arm_dpm.h +++ b/src/target/arm_dpm.h @@ -136,4 +136,18 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp); void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar); +/* Subset of DSCR bits; see ARMv7a arch spec section C10.3.1. + * Not all v7 bits are valid in v6. + */ +#define DSCR_CORE_HALTED (1 << 0) +#define DSCR_CORE_RESTARTED (1 << 1) +#define DSCR_ITR_EN (1 << 13) +#define DSCR_HALT_DBG_MODE (1 << 14) +#define DSCR_MON_DBG_MODE (1 << 15) +#define DSCR_INSTR_COMP (1 << 24) +#define DSCR_DTR_TX_FULL (1 << 29) +#define DSCR_DTR_RX_FULL (1 << 30) + +#define DSCR_ENTRY(dscr) (((dscr) >> 2) & 0xf) + #endif /* __ARM_DPM_H */ |