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| author | Tomas Vanek <vanekt@fbl.cz> | 2018-02-23 00:03:20 +0100 |
|---|---|---|
| committer | Matthias Welwarsky <matthias@welwarsky.de> | 2018-04-07 20:31:37 +0100 |
| commit | 414213a5ead0e34dec7f72748dbd5c721cb92c09 (patch) | |
| tree | a57948de1a90c3760bfbf77368f14246eaf15d6f /src/target/arm_adi_v5.h | |
| parent | 2e2bb14b276f5bd973308dcfabd1b8018e187243 (diff) | |
| download | riscv-openocd-414213a5ead0e34dec7f72748dbd5c721cb92c09.zip riscv-openocd-414213a5ead0e34dec7f72748dbd5c721cb92c09.tar.gz riscv-openocd-414213a5ead0e34dec7f72748dbd5c721cb92c09.tar.bz2 | |
target/arm_adi_v5: extend apcsw command to accept arbitrary bits
apcsw command was limited to SPROT bit only.
Now user can manipulate any bit except size and addrinc fields.
Can be used e.g. to set bus signal 'cacheable' on Cortex-M7
Change-Id: Ia1c22b208e46d1653136f6faa5a7aaab036de7aa
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4431
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'src/target/arm_adi_v5.h')
| -rw-r--r-- | src/target/arm_adi_v5.h | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h index bc56116..22c3166 100644 --- a/src/target/arm_adi_v5.h +++ b/src/target/arm_adi_v5.h @@ -112,13 +112,16 @@ #define CSW_ADDRINC_PACKED (2UL << 4) #define CSW_DEVICE_EN (1UL << 6) #define CSW_TRIN_PROG (1UL << 7) +/* all fields in bits 12 and above are implementation-defined! */ #define CSW_SPIDEN (1UL << 23) -/* 30:24 - implementation-defined! */ -#define CSW_HPROT (1UL << 25) /* ? */ -#define CSW_MASTER_DEBUG (1UL << 29) /* ? */ +#define CSW_HPROT1 (1UL << 25) /* AHB: Privileged */ +#define CSW_MASTER_DEBUG (1UL << 29) /* AHB: set HMASTER signals to AHB-AP ID */ #define CSW_SPROT (1UL << 30) #define CSW_DBGSWENABLE (1UL << 31) +/* initial value of csw_default used for MEM-AP transfers */ +#define CSW_DEFAULT (CSW_HPROT1 | CSW_MASTER_DEBUG | CSW_DBGSWENABLE) + /* Fields of the MEM-AP's IDR register */ #define IDR_REV (0xFUL << 28) #define IDR_JEP106 (0x7FFUL << 17) |