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| author | Megan Wachs <megan@sifive.com> | 2018-05-17 16:35:25 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-05-17 16:35:25 -0700 |
| commit | 3344db3d0aef8f3b8c033cb2a098e9ca15e8615c (patch) | |
| tree | bdf25d2e31ece8972c75b5900e6a16d16ebbafdc /src/target/arm.h | |
| parent | 06e6c2297fa6711d9a4f8914581b2b558fe1d823 (diff) | |
| parent | 802c3b4003992455a6480b0aecb48f54e84a8bfc (diff) | |
| download | riscv-openocd-3344db3d0aef8f3b8c033cb2a098e9ca15e8615c.zip riscv-openocd-3344db3d0aef8f3b8c033cb2a098e9ca15e8615c.tar.gz riscv-openocd-3344db3d0aef8f3b8c033cb2a098e9ca15e8615c.tar.bz2 | |
Merge pull request #255 from riscv/reset-unexpected-check
riscv: remove unexpected check during reset
Diffstat (limited to 'src/target/arm.h')
0 files changed, 0 insertions, 0 deletions