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| author | Andreas Färber <afaerber@suse.de> | 2016-05-14 20:21:49 +0200 |
|---|---|---|
| committer | Freddie Chopin <freddie.chopin@gmail.com> | 2016-05-20 21:38:03 +0100 |
| commit | 0c8ec7c826c60391034fe5f0ea90f8538ac94b38 (patch) | |
| tree | 3f1bf74454812f49bf5f2994a6eddc41677c99d8 /src/rtos | |
| parent | f630fac2e72af502d12139fdc864a01a4da7c868 (diff) | |
| download | riscv-openocd-0c8ec7c826c60391034fe5f0ea90f8538ac94b38.zip riscv-openocd-0c8ec7c826c60391034fe5f0ea90f8538ac94b38.tar.gz riscv-openocd-0c8ec7c826c60391034fe5f0ea90f8538ac94b38.tar.bz2 | |
Fix spelling of ARM Cortex
It's Cortex-Xn, not Cortex Xn or cortex xn or cortex-xn or CORTEX-Xn
or CortexXn. Further it's Cortex-M0+, not M0plus.
Cf. http://www.arm.com/products/processors/index.php
Consistently write it the official way, so that it stops propagating.
Originally spotted in the documentation, it mainly affects code comments
but also Atmel SAM3/SAM4/SAMV, NiietCM4 and SiM3x flash driver output.
Found via:
git grep -i "Cortex "
git grep -i "Cortex-" | grep -v "Cortex-" | grep -v ".cpu"
git grep -i "CortexM"
Change-Id: Ic7b6ca85253e027f6f0f751c628d1a2a391fe914
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3483
Tested-by: jenkins
Reviewed-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Diffstat (limited to 'src/rtos')
| -rw-r--r-- | src/rtos/ChibiOS.c | 4 | ||||
| -rw-r--r-- | src/rtos/FreeRTOS.c | 2 | ||||
| -rw-r--r-- | src/rtos/mqx.c | 2 | ||||
| -rw-r--r-- | src/rtos/rtos_standard_stackings.c | 2 |
4 files changed, 5 insertions, 5 deletions
diff --git a/src/rtos/ChibiOS.c b/src/rtos/ChibiOS.c index 8439386..be91be5 100644 --- a/src/rtos/ChibiOS.c +++ b/src/rtos/ChibiOS.c @@ -226,7 +226,7 @@ static int ChibiOS_update_stacking(struct rtos *rtos) /* Sometimes the stacking can not be determined only by looking at the * target name but only a runtime. * - * For example, this is the case for cortex-m4 targets and ChibiOS which + * For example, this is the case for Cortex-M4 targets and ChibiOS which * only stack the FPU registers if it is enabled during ChibiOS build. * * Terminating which stacking is used is target depending. @@ -248,7 +248,7 @@ static int ChibiOS_update_stacking(struct rtos *rtos) struct ChibiOS_params *param; param = (struct ChibiOS_params *) rtos->rtos_specific_params; - /* Check for armv7m with *enabled* FPU, i.e. a Cortex M4 */ + /* Check for armv7m with *enabled* FPU, i.e. a Cortex-M4 */ struct armv7m_common *armv7m_target = target_to_armv7m(rtos->target); if (is_armv7m(armv7m_target)) { if (armv7m_target->fp_feature == FPv4_SP) { diff --git a/src/rtos/FreeRTOS.c b/src/rtos/FreeRTOS.c index 9313773..a58eed1 100644 --- a/src/rtos/FreeRTOS.c +++ b/src/rtos/FreeRTOS.c @@ -430,7 +430,7 @@ static int FreeRTOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, ch thread_id + param->thread_stack_offset, stack_ptr); - /* Check for armv7m with *enabled* FPU, i.e. a Cortex M4F */ + /* Check for armv7m with *enabled* FPU, i.e. a Cortex-M4F */ int cm4_fpu_enabled = 0; struct armv7m_common *armv7m_target = target_to_armv7m(rtos->target); if (is_armv7m(armv7m_target)) { diff --git a/src/rtos/mqx.c b/src/rtos/mqx.c index 272658c..f0f419c 100644 --- a/src/rtos/mqx.c +++ b/src/rtos/mqx.c @@ -109,7 +109,7 @@ static int mqx_valid_address_check( enum mqx_arch arch_type = ((struct mqx_params *)rtos->rtos_specific_params)->target_arch; const char * targetname = ((struct mqx_params *)rtos->rtos_specific_params)->target_name; - /* Cortex M address range */ + /* Cortex-M address range */ if (arch_type == mqx_arch_cortexm) { if ( /* code and sram area */ diff --git a/src/rtos/rtos_standard_stackings.c b/src/rtos/rtos_standard_stackings.c index 7d72b4e..32f82a9 100644 --- a/src/rtos/rtos_standard_stackings.c +++ b/src/rtos/rtos_standard_stackings.c @@ -182,7 +182,7 @@ int64_t rtos_generic_stack_align8(struct target *target, stacking, stack_ptr, 8); } -/* The Cortex M3 will indicate that an alignment adjustment +/* The Cortex-M3 will indicate that an alignment adjustment * has been done on the stack by setting bit 9 of the stacked xPSR * register. In this case, we can just add an extra 4 bytes to get * to the program stack. Note that some places in the ARM documentation |