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| author | Evan Hunter <ehunter@broadcom.com> | 2014-11-21 17:42:23 +0000 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2015-01-15 23:16:06 +0000 |
| commit | d25b43b1635df370424a57d4475ba4ca46f43758 (patch) | |
| tree | b1765ba6fd37519bba794c742de24af45720638d /src/jtag/core.c | |
| parent | d12fa18bd91133bca0fcc4bfd05bfb8c7d86b45c (diff) | |
| download | riscv-openocd-d25b43b1635df370424a57d4475ba4ca46f43758.zip riscv-openocd-d25b43b1635df370424a57d4475ba4ca46f43758.tar.gz riscv-openocd-d25b43b1635df370424a57d4475ba4ca46f43758.tar.bz2 | |
jtag: Avoid extra SRSTn resets when connecting
Previously the jtag_add_reset(1, 0) caused the processor to be released,
and if SRSTn existed then it would then be reset again two lines later.
Change-Id: I58b7a12607f46f83caa7ed3b3cebc4195eb51ef6
Signed-off-by: Evan Hunter <ehunter@broadcom.com>
Reviewed-on: http://openocd.zylin.com/2398
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'src/jtag/core.c')
| -rw-r--r-- | src/jtag/core.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/jtag/core.c b/src/jtag/core.c index 04b0fc6..eb01abc 100644 --- a/src/jtag/core.c +++ b/src/jtag/core.c @@ -1552,11 +1552,12 @@ int jtag_init_reset(struct command_context *cmd_ctx) * REVISIT once Tcl code can read the reset_config modes, this won't * need to be a C routine at all... */ - jtag_add_reset(1, 0); /* TAP_RESET, using TMS+TCK or TRST */ if (jtag_reset_config & RESET_HAS_SRST) { jtag_add_reset(1, 1); if ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0) jtag_add_reset(0, 1); + } else { + jtag_add_reset(1, 0); /* TAP_RESET, using TMS+TCK or TRST */ } /* some targets enable us to connect with srst asserted */ |