flash: fix typos and duplicated words

Fix typos and duplicated words in comments and strings.

Change-Id: I64282c7018462deefeeb8e5f4d0d81942425b3fc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5758
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Christopher Head <chead@zaber.com>

6 files changed, 29 insertions, 29 deletions

diff --git a/src/flash/nand/driver.h b/src/flash/nand/driver.h
index 2182a77..690ee91 100644
--- a/src/flash/nand/driver.h
+++ b/src/flash/nand/driver.h
@@ -94,7 +94,7 @@ typedef int (*nand_driver_walker_t)(struct nand_flash_controller *c, void *);
  * Walk the list of drivers, encapsulating the data structure type.
  * Application state/context can be passed through the @c x pointer.
  * @param f The callback function to invoke for each function.
- * @param x For use as private data storate, passed directly to @c f.
+ * @param x For use as private data storage, passed directly to @c f.
  * @returns ERROR_OK if successful, or the non-zero return value of @c f.
  * This allows a walker to terminate the loop early.
  */
diff --git a/src/flash/nand/fileio.c b/src/flash/nand/fileio.c
index f65f957..1279e45 100644
--- a/src/flash/nand/fileio.c
+++ b/src/flash/nand/fileio.c
@@ -206,7 +206,7 @@ int nand_fileio_read(struct nand_device *nand, struct nand_fileio_state *s)
 	} else if (s->oob_format & NAND_OOB_SW_ECC_KW)   {
 		/*
 		 * In this case eccpos is not used as
-		 * the ECC data is always stored contigously
+		 * the ECC data is always stored contiguously
 		 * at the end of the OOB area.  It consists
 		 * of 10 bytes per 512-byte data block.
 		 */
diff --git a/src/flash/nand/lpc3180.c b/src/flash/nand/lpc3180.c
index 389c18a..97bd7a3 100644
--- a/src/flash/nand/lpc3180.c
+++ b/src/flash/nand/lpc3180.c
@@ -232,7 +232,7 @@ static int lpc3180_init(struct nand_device *nand)
 		/* FLASHCLK_CTRL = 0x05 (enable clock for SLC flash controller) */
 		target_write_u32(target, 0x400040c8, 0x05);
 
-		/* after reset set other registers of SLC so reset calling is here at the begining*/
+		/* after reset set other registers of SLC so reset calling is here at the beginning */
 		lpc3180_reset(nand);
 
 		/* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst enabled,
diff --git a/src/flash/nand/lpc32xx.c b/src/flash/nand/lpc32xx.c
index 058d9a5..d516522 100644
--- a/src/flash/nand/lpc32xx.c
+++ b/src/flash/nand/lpc32xx.c
@@ -42,7 +42,7 @@ extern int nand_correct_data(struct nand_device *nand, u_char *dat,
  * read/write data to the SLC controller.
  * - DMA descriptors will be put at start of working area,
  * - Hardware generated ECC will be stored at ECC_OFFS
- * - OOB wil be read/written from/to SPARE_OFFS
+ * - OOB will be read/written from/to SPARE_OFFS
  * - Actual page data will be read from/to DATA_OFFS
  * There are unused holes between the used areas.
  */
@@ -317,7 +317,7 @@ static int lpc32xx_init(struct nand_device *nand)
 		}
 
 		/* after reset set other registers of SLC,
-		 * so reset calling is here at the begining
+		 * so reset calling is here at the beginning
 		 */
 		retval = lpc32xx_reset(nand);
 		if (ERROR_OK != retval)
@@ -769,7 +769,7 @@ static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size,
 	 * 2. Copy generated ECC data from Register to Spare Area
 	 * 3. X'fer next 256 bytes of data from Memory to Flash.
 	 * 4. Copy generated ECC data from Register to Spare Area.
-	 * 5. X'fer 16 byets of Spare area from Memory to Flash.
+	 * 5. X'fer 16 bytes of Spare area from Memory to Flash.
 	 * Read Operation Sequence for Small Block NAND
 	 * ----------------------------------------------------------
 	 * 1. X'fer 256 bytes of data from Flash to Memory.
@@ -779,13 +779,13 @@ static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size,
 	 * 5. X'fer 16 bytes of Spare area from Flash to Memory.
 	 * Write Operation Sequence for Large Block NAND
 	 * ----------------------------------------------------------
-	 * 1. Steps(1-4) of Write Operations repeate for four times
+	 * 1. Steps(1-4) of Write Operations repeated for four times
 	 * which generates 16 DMA descriptors to X'fer 2048 bytes of
 	 * data & 32 bytes of ECC data.
 	 * 2. X'fer 64 bytes of Spare area from Memory to Flash.
 	 * Read Operation Sequence for Large Block NAND
 	 * ----------------------------------------------------------
-	 * 1. Steps(1-4) of Read Operations repeate for four times
+	 * 1. Steps(1-4) of Read Operations repeated for four times
 	 * which generates 16 DMA descriptors to X'fer 2048 bytes of
 	 * data & 32 bytes of ECC data.
 	 * 2. X'fer 64 bytes of Spare area from Flash to Memory.
@@ -842,7 +842,7 @@ static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size,
 	 * 2. Copy generated ECC data from Register to Spare Area
 	 * 3. X'fer next 256 bytes of data from Memory to Flash.
 	 * 4. Copy generated ECC data from Register to Spare Area.
-	 * 5. X'fer 16 byets of Spare area from Memory to Flash.
+	 * 5. X'fer 16 bytes of Spare area from Memory to Flash.
 	 * Read Operation Sequence for Small Block NAND
 	 * ----------------------------------------------------------
 	 * 1. X'fer 256 bytes of data from Flash to Memory.
@@ -852,13 +852,13 @@ static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size,
 	 * 5. X'fer 16 bytes of Spare area from Flash to Memory.
 	 * Write Operation Sequence for Large Block NAND
 	 * ----------------------------------------------------------
-	 * 1. Steps(1-4) of Write Operations repeate for four times
+	 * 1. Steps(1-4) of Write Operations repeated for four times
 	 * which generates 16 DMA descriptors to X'fer 2048 bytes of
 	 * data & 32 bytes of ECC data.
 	 * 2. X'fer 64 bytes of Spare area from Memory to Flash.
 	 * Read Operation Sequence for Large Block NAND
 	 * ----------------------------------------------------------
-	 * 1. Steps(1-4) of Read Operations repeate for four times
+	 * 1. Steps(1-4) of Read Operations repeated for four times
 	 * which generates 16 DMA descriptors to X'fer 2048 bytes of
 	 * data & 32 bytes of ECC data.
 	 * 2. X'fer 64 bytes of Spare area from Flash to Memory.
@@ -1044,7 +1044,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand,
 
 	target_mem_base = pworking_area->address;
 	/*
-	 * Skip writting page which has all 0xFF data as this will
+	 * Skip writing page which has all 0xFF data as this will
 	 * generate 0x0 value.
 	 */
 	if (data && !oob) {
@@ -1102,7 +1102,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand,
 			return retval;
 		}
 
-		/* Write first decriptor to DMA controller */
+		/* Write first descriptor to DMA controller */
 		retval = target_write_memory(target, 0x31000100, 4,
 				sizeof(dmac_ll_t) / 4,
 				(uint8_t *)dmalist);
@@ -1159,7 +1159,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand,
 		return retval;
 	}
 
-	/* Write OOB decriptor to DMA controller */
+	/* Write OOB descriptor to DMA controller */
 	retval = target_write_memory(target, 0x31000100, 4,
 			sizeof(dmac_ll_t) / 4,
 			(uint8_t *)(&dmalist[nll-1]));
@@ -1487,7 +1487,7 @@ static int lpc32xx_read_page_slc(struct nand_device *nand,
 		return retval;
 	}
 
-	/* Write first decriptor to DMA controller */
+	/* Write first descriptor to DMA controller */
 	retval = target_write_memory(target, 0x31000100, 4,
 			sizeof(dmac_ll_t) / 4, (uint8_t *)dmalist);
 	if (ERROR_OK != retval) {
diff --git a/src/flash/nand/mx3.c b/src/flash/nand/mx3.c
index da141b7..abeaf15 100644
--- a/src/flash/nand/mx3.c
+++ b/src/flash/nand/mx3.c
@@ -149,7 +149,7 @@ static int imx31_init(struct nand_device *nand)
 		uint32_t gpr_register_content;
 		target_read_u32(target, MX3_GPR, &gpr_register_content);
 		if (gpr_register_content & 0x00000060) {
-			LOG_ERROR("pins mode overrided by GPR");
+			LOG_ERROR("pins mode overridden by GPR");
 			return ERROR_FAIL;
 		}
 	}
@@ -414,10 +414,10 @@ static int imx31_write_page(struct nand_device *nand, uint32_t page,
 		if (oob) {
 			if (mx3_nf_info->flags.hw_ecc_enabled) {
 				/*
-				 * part of spare block will be overrided by hardware
+				 * part of spare block will be overridden by hardware
 				 * ECC generator
 				 */
-				LOG_DEBUG("part of spare block will be overrided by hardware ECC generator");
+				LOG_DEBUG("part of spare block will be overridden by hardware ECC generator");
 			}
 			target_write_buffer(target, MX3_NF_SPARE_BUFFER0, oob_size, oob);
 		}
@@ -530,7 +530,7 @@ static int initialize_nf_controller(struct nand_device *nand)
 	struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
 	struct target *target = nand->target;
 	/*
-	* resets NAND flash controller in zero time ? I dont know.
+	* resets NAND flash controller in zero time ? I don't know.
 	*/
 	target_write_u16(target, MX3_NF_CFG1, MX3_NF_BIT_RESET_EN);
 	{
@@ -680,18 +680,18 @@ static int do_data_output(struct nand_device *nand)
 				target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status);
 				switch (ecc_status & 0x000c) {
 				case 1 << 2:
-					LOG_DEBUG("main area readed with 1 (correctable) error");
+					LOG_DEBUG("main area read with 1 (correctable) error");
 					break;
 				case 2 << 2:
-					LOG_DEBUG("main area readed with more than 1 (incorrectable) error");
+					LOG_DEBUG("main area read with more than 1 (incorrectable) error");
 					return ERROR_NAND_OPERATION_FAILED;
 				}
 				switch (ecc_status & 0x0003) {
 				case 1:
-					LOG_DEBUG("spare area readed with 1 (correctable) error");
+					LOG_DEBUG("spare area read with 1 (correctable) error");
 					break;
 				case 2:
-					LOG_DEBUG("main area readed with more than 1 (incorrectable) error");
+					LOG_DEBUG("main area read with more than 1 (incorrectable) error");
 					return ERROR_NAND_OPERATION_FAILED;
 				}
 			}
diff --git a/src/flash/nand/mxc.c b/src/flash/nand/mxc.c
index ee093c0..bc2ae93 100644
--- a/src/flash/nand/mxc.c
+++ b/src/flash/nand/mxc.c
@@ -136,7 +136,7 @@ NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command)
 		(nand->target->endianness == TARGET_LITTLE_ENDIAN);
 
 	/*
-	 * should factory bad block indicator be swaped
+	 * should factory bad block indicator be swapped
 	 * as a workaround for how the nfc handles pages.
 	 */
 	if (CMD_ARGC > 4 && strcmp(CMD_ARGV[4], "biswap") == 0) {
@@ -181,7 +181,7 @@ static const struct command_registration mxc_sub_command_handlers[] = {
 		.name = "biswap",
 		.mode = COMMAND_EXEC,
 		.handler = handle_mxc_biswap_command,
-		.help = "Turns on/off bad block information swaping from main area, "
+		.help = "Turns on/off bad block information swapping from main area, "
 			"without parameter query status.",
 		.usage = "bank_id ['enable'|'disable']",
 	},
@@ -400,7 +400,7 @@ static int mxc_command(struct nand_device *nand, uint8_t command)
 			mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
 			break;
 		default:
-			/* Ohter command use the default 'One page data out' FDO */
+			/* Other command use the default 'One page data out' FDO */
 			mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
 			break;
 	}
@@ -502,10 +502,10 @@ static int mxc_write_page(struct nand_device *nand, uint32_t page,
 	if (oob) {
 		if (mxc_nf_info->flags.hw_ecc_enabled) {
 			/*
-			 * part of spare block will be overrided by hardware
+			 * part of spare block will be overridden by hardware
 			 * ECC generator
 			 */
-			LOG_DEBUG("part of spare block will be overrided "
+			LOG_DEBUG("part of spare block will be overridden "
 				"by hardware ECC generator");
 		}
 		if (nfc_is_v1())
@@ -710,7 +710,7 @@ static int initialize_nf_controller(struct nand_device *nand)
 	uint16_t work_mode = 0;
 	uint16_t temp;
 	/*
-	 * resets NAND flash controller in zero time ? I dont know.
+	 * resets NAND flash controller in zero time ? I don't know.
 	 */
 	target_write_u16(target, MXC_NF_CFG1, MXC_NF_BIT_RESET_EN);
 	if (mxc_nf_info->mxc_version == MXC_VERSION_MX27)