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| author | Marek Vasut <marek.vasut@gmail.com> | 2021-05-30 17:34:10 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2021-06-26 14:39:30 +0100 |
| commit | 7c8a068a40ab81abf0938c3e091bf4e927a47bcd (patch) | |
| tree | 34c359fc98e3dc65ceecf881578906bc247e4009 /git-hooks/commit-msg | |
| parent | a38a0afd17d943b8bbc046f5fcfbf150871557a2 (diff) | |
| download | riscv-openocd-7c8a068a40ab81abf0938c3e091bf4e927a47bcd.zip riscv-openocd-7c8a068a40ab81abf0938c3e091bf4e927a47bcd.tar.gz riscv-openocd-7c8a068a40ab81abf0938c3e091bf4e927a47bcd.tar.bz2 | |
tcl/target: Add support for Renesas R8A779A0 V3U SoC
The V3U SoC is unique in that it now has 8x CA76 and CR52,
while the previous SoCs had CA57/CA53/CR7 . This can still
be handled without too complex modifications to the gen3
configuration file, so add the logic to handle it there.
Change-Id: I7ab33eacc1fd379d369988d3d6690d2e82346c7e
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/6314
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'git-hooks/commit-msg')
0 files changed, 0 insertions, 0 deletions