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| author | Tim Newsome <tim@sifive.com> | 2018-07-17 14:09:55 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2018-07-17 14:09:55 -0700 |
| commit | bda019bdc2c56e3a7e231c22b9b55b44f5f7e9c0 (patch) | |
| tree | 338c8cc34cabf4e3b7cbb803edd2a6d4d3826a53 /doc | |
| parent | 9c6aedac7fe7949f8bc0431ecc00e609c60830e5 (diff) | |
| download | riscv-openocd-bda019bdc2c56e3a7e231c22b9b55b44f5f7e9c0.zip riscv-openocd-bda019bdc2c56e3a7e231c22b9b55b44f5f7e9c0.tar.gz riscv-openocd-bda019bdc2c56e3a7e231c22b9b55b44f5f7e9c0.tar.bz2 | |
Explain what RISC-V targets are supported.
Change-Id: I4c50a1507ca0fcbdd8340a851e8ab0ae1feca1a2
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/openocd.texi | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index 7f29fdc..bf42ab1 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -8903,8 +8903,11 @@ Display all registers in @emph{group}. @section RISC-V Architecture @uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG -debug of targets that implement version 0.11 and 0.13 of the RISC-V Debug -Specification. +debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 32 +harts. (It's possible to increase this limit to 1024 by changing +RISCV_MAX_HARTS in riscv.h.) OpenOCD primarily supports 0.13 of the RISC-V +Debug Specification, but there is also support for legacy targets that +implement version 0.11. @subsection RISC-V Terminology |