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author | Antonio Borneo <borneo.antonio@gmail.com> | 2022-10-16 23:56:23 +0200 |
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committer | Antonio Borneo <borneo.antonio@gmail.com> | 2022-10-21 18:14:46 +0000 |
commit | b8735bbf7ed7eedb0590edbf2a22929b401887ba (patch) | |
tree | 8978e3513af84fa75f9a50935c2a0f2bd3b19378 /doc | |
parent | 1f7d58daeef9d695529af0cc41c52095c8936c80 (diff) | |
download | riscv-openocd-b8735bbf7ed7eedb0590edbf2a22929b401887ba.zip riscv-openocd-b8735bbf7ed7eedb0590edbf2a22929b401887ba.tar.gz riscv-openocd-b8735bbf7ed7eedb0590edbf2a22929b401887ba.tar.bz2 |
doc: fix riscv commands
- Fix the declaration of riscv command 'set_mem_access'.
- Remove non existing riscv command 'set_scratch_ram'.
- Add riscv commands 'info', 'reset_delays'; copy the description
from the 'help' text.
- Don't add riscv commands 'set_prefer_sba' and 'test_sba_config_reg'
as they are marked as deprecated.
- Ensure that 'test_sba_config_reg' prints a deprecation warning
when used.
Change-Id: I39dc3aec4e7f13b69ac19685f1b593790acdde83
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Jan Matyas <matyas@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7268
Reviewed-by: Tim Newsome <tim@sifive.com>
Tested-by: jenkins
Diffstat (limited to 'doc')
-rw-r--r-- | doc/openocd.texi | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index ba495cc..6321bf7 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -10649,6 +10649,16 @@ $_TARGETNAME expose_custom 32=myregister @end example @end deffn +@deffn {Command} {riscv info} +Displays some information OpenOCD detected about the target. +@end deffn + +@deffn {Command} {riscv reset_delays} [wait] +OpenOCD learns how many Run-Test/Idle cycles are required between scans to avoid +encountering the target being busy. This command resets those learned values +after `wait` scans. It's only useful for testing OpenOCD itself. +@end deffn + @deffn {Command} {riscv set_command_timeout_sec} [seconds] Set the wall-clock timeout (in seconds) for individual commands. The default should work fine for all but the slowest targets (eg. simulators). @@ -10659,12 +10669,7 @@ Set the maximum time to wait for a hart to come out of reset after reset is deasserted. @end deffn -@deffn {Command} {riscv set_scratch_ram} none|[address] -Set the address of 16 bytes of scratch RAM the debugger can use, or 'none'. -This is used to access 64-bit floating point registers on 32-bit targets. -@end deffn - -@deffn Command {riscv set_mem_access} method1 [method2] [method3] +@deffn {Command} {riscv set_mem_access} method1 [method2] [method3] Specify which RISC-V memory access method(s) shall be used, and in which order of priority. At least one method must be specified. |