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authorEvan Hunter <ehunter@broadcom.com>2015-07-17 12:41:12 +0100
committerFreddie Chopin <freddie.chopin@gmail.com>2015-11-07 20:36:13 +0000
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Cortex A/R : Allow interrupt disable during single-step
Example usage: cortex_a maskisr on cortex_a maskisr off cortex_r maskisr on cortex_r maskisr off Change-Id: I799288d9b848a06f561ba29ec1eb8e5eeace5685 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/2876 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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-rw-r--r--doc/openocd.texi4
1 files changed, 4 insertions, 0 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi
index eb4bd4e..76c9766 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -7615,6 +7615,10 @@ Initialize core debug
Enables debug by unlocking the Software Lock and clearing sticky powerdown indications
@end deffn
+@deffn Command {cortex_r maskisr} [@option{on}|@option{off}]
+Selects whether interrupts will be processed when single stepping
+@end deffn
+
@subsection ARMv7-M specific commands
@cindex tracing