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| author | Dean Glazeski <dnglaze@gmail.com> | 2009-12-09 12:40:54 -0600 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-19 13:26:33 -0800 |
| commit | 3ac2a440419a52752a5e11eba8ab2722a1fe73bf (patch) | |
| tree | c2b9cc1b558654e26cdc146431e4504c2f32e757 /doc | |
| parent | 28f8e9dfb7bfaf87957c95790c3ffe5d9fbd8834 (diff) | |
| download | riscv-openocd-3ac2a440419a52752a5e11eba8ab2722a1fe73bf.zip riscv-openocd-3ac2a440419a52752a5e11eba8ab2722a1fe73bf.tar.gz riscv-openocd-3ac2a440419a52752a5e11eba8ab2722a1fe73bf.tar.bz2 | |
AT91SAM9 NAND flash driver.
This creates the TCL interface for configuring an AT91SAM9 NAND flash
controller and implements the necessary functions to correctly work with
a NAND flash device connected to the chip. This includes updates to the
driver list and the Makefile.am to support building the driver and also
houses the documentation update in openocd.texi.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/openocd.texi | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index d9cb4ea..4244a1e 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -4812,6 +4812,41 @@ As noted above, the @command{nand device} command allows driver-specific options and behaviors. Some controllers also activate controller-specific commands. +@deffn {NAND Driver} at91sam9 +This driver handles the NAND controllers found on AT91SAM9 family chips from +Atmel. It takes two extra parameters: address of the NAND chip; +address of the ECC controller. +@example +nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800 +@end example +AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and +@code{read_page} methods are used to utilize the ECC hardware unless they are +disabled by using the @command{nand raw_access} command. There are four +additional commands that are needed to fully configure the AT91SAM9 NAND +controller. Two are optional; most boards use the same wiring for ALE/CLE: +@deffn Command {at91sam9 cle} num addr_line +Configure the address line used for latching commands. The @var{num} +parameter is the value shown by @command{nand list}. +@end deffn +@deffn Command {at91sam9 ale} num addr_line +Configure the address line used for latching addresses. The @var{num} +parameter is the value shown by @command{nand list}. +@end deffn + +For the next two commands, it is assumed that the pins have already been +properly configured for input or output. +@deffn Command {at91sam9 rdy_busy} num pio_base_addr pin +Configure the RDY/nBUSY input from the NAND device. The @var{num} +parameter is the value shown by @command{nand list}. @var{pio_base_addr} +is the base address of the PIO controller and @var{pin} is the pin number. +@end deffn +@deffn Command {at91sam9 ce} num pio_base_addr pin +Configure the chip enable input to the NAND device. The @var{num} +parameter is the value shown by @command{nand list}. @var{pio_base_addr} +is the base address of the PIO controller and @var{pin} is the pin number. +@end deffn +@end deffn + @deffn {NAND Driver} davinci This driver handles the NAND controllers found on DaVinci family chips from Texas Instruments. |