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authorDaniel Anselmi <danselmi@gmx.ch>2022-12-17 13:11:30 +0100
committerAntonio Borneo <borneo.antonio@gmail.com>2023-09-23 14:36:14 +0000
commiteb22a37b42a7944694243b690bfbd736e1ef52e8 (patch)
tree7cd75412ecc6e14820f730d73202de21b838fbc9 /doc
parent198a914cf99a8602a05227ac5327a805714e4b87 (diff)
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pld: harmonize refresh commands
add refresh command for lattice devices rename gowin reprogram to refresh rename virtex2 program to refresh Change-Id: I9da83a614b96da3e947ac4608b0a291b1d126914 Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7839 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'doc')
-rw-r--r--doc/openocd.texi12
1 files changed, 8 insertions, 4 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 7ad48c8..2d59238 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -8764,8 +8764,8 @@ Change values for boundary scan instructions selecting the registers USER1 to US
Description of the arguments can be found at command @command{virtex2 set_instr_codes}.
@end deffn
-@deffn {Command} {virtex2 program} pld_name
-Load the bitstream from external memory for FPGA @var{pld_name}. A.k.a. refresh.
+@deffn {Command} {virtex2 refresh} pld_name
+Load the bitstream from external memory for FPGA @var{pld_name}. A.k.a. program.
@end deffn
@end deffn
@@ -8796,6 +8796,10 @@ for FPGA @var{pld_name} with value @var{val}.
Set the length of the register for the preload. This is needed when the JTAG ID of the device is not known by openocd (newer NX devices).
The load command for the FPGA @var{pld_name} will use a length for the preload of @var{length}.
@end deffn
+
+@deffn {Command} {lattice refresh} pld_name
+Load the bitstream from external memory for FPGA @var{pld_name}. A.k.a program.
+@end deffn
@end deffn
@@ -8850,9 +8854,9 @@ Reads and displays the user register
for FPGA @var{pld_name}.
@end deffn
-@deffn {Command} {gowin reload} pld_name
+@deffn {Command} {gowin refresh} pld_name
Load the bitstream from external memory for
-FPGA @var{pld_name}. A.k.a. refresh.
+FPGA @var{pld_name}. A.k.a. reload.
@end deffn
@end deffn