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| author | Matthias Welwarsky <matthias.welwarsky@sysgo.com> | 2017-02-27 17:10:19 +0100 |
|---|---|---|
| committer | Matthias Welwarsky <matthias@welwarsky.de> | 2018-01-16 09:05:41 +0000 |
| commit | b3d29cb5441ee5d38e8f7b561a58f03eb269dbe4 (patch) | |
| tree | 2b0d763407ddac3be85ff4b7596e315b1fcb3eb3 /doc | |
| parent | f7836bbc75586666d639edd1cf39a871c434d980 (diff) | |
| download | riscv-openocd-b3d29cb5441ee5d38e8f7b561a58f03eb269dbe4.zip riscv-openocd-b3d29cb5441ee5d38e8f7b561a58f03eb269dbe4.tar.gz riscv-openocd-b3d29cb5441ee5d38e8f7b561a58f03eb269dbe4.tar.bz2 | |
aarch64: add 'maskisr' command
Allow to configure ISR masking during single-step and add
handling for stepping over WFI with ISR masked.
Change-Id: I7918be7bcda6a1d9badac44fc36c59b52f662fef
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4023
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/openocd.texi | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index 431f11c..483b27b 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -8418,6 +8418,11 @@ halting or resuming of all cores in the group. The command @code{target smp} def group. With SMP handling disabled, all targets need to be treated individually. @end deffn +@deffn Command {aarch64 maskisr} [@option{on}|@option{off}] +Selects whether interrupts will be processed when single stepping. The default configuration is +@option{on}. +@end deffn + @section Intel Architecture Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32 |