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author | Antonio Borneo <borneo.antonio@gmail.com> | 2020-04-26 01:39:16 +0200 |
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committer | Antonio Borneo <borneo.antonio@gmail.com> | 2020-05-09 14:37:25 +0100 |
commit | 3a28cdc7cb790e388f0e142510858bee0b642597 (patch) | |
tree | 0dbc93ef5a084387475384479c9707019a0dfa23 /doc/openocd.texi | |
parent | 307ee6db473b3e92597ee69863f5428a37a8a941 (diff) | |
download | riscv-openocd-3a28cdc7cb790e388f0e142510858bee0b642597.zip riscv-openocd-3a28cdc7cb790e388f0e142510858bee0b642597.tar.gz riscv-openocd-3a28cdc7cb790e388f0e142510858bee0b642597.tar.bz2 |
doc: fix typo and spelling
Identified by checkpatch script from Linux kernel v5.7-rc1 using
the command
find doc/ -type f -exec ./tools/scripts/checkpatch.pl \
-q --types TYPO_SPELLING --strict -f {} \;
Change-Id: I1269ac966027439e16eb6e63179e43925bec37fa
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5614
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
Diffstat (limited to 'doc/openocd.texi')
-rw-r--r-- | doc/openocd.texi | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index f3f963e..ef77993 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -1474,7 +1474,7 @@ While the default is normally provided by the chip manufacturer, board files may need to distinguish between instances of a chip. @item @code{ENDIAN} ... By default @option{little} - although chips may hard-wire @option{big}. -Chips that can't change endianess don't need to use this variable. +Chips that can't change endianness don't need to use this variable. @item @code{CPUTAPID} ... When OpenOCD examines the JTAG chain, it can be told verify the chips against the JTAG IDCODE register. @@ -6459,7 +6459,7 @@ code. @end deffn @deffn Command {nrf5 info} -Decodes and shows informations from FICR and UICR registers. +Decodes and shows information from FICR and UICR registers. @end deffn @end deffn @@ -9774,7 +9774,7 @@ or a custom types described with @command{arc add-reg-type-[flags|struct]}. @item @code{-g} @* If specified then this is a "general" register. General registers are always read by OpenOCD on context save (when core has just been halted) and is always -transfered to GDB client in a response to g-packet. Contrary to this, +transferred to GDB client in a response to g-packet. Contrary to this, non-general registers are read and sent to GDB client on-demand. In general it is not recommended to apply this option to custom registers. @@ -9815,7 +9815,7 @@ therefore it is unsafe to use if that register can be operated by other means. @end deffn @deffn {Command} {arc jtag set-core-reg} regnum value -This command is similiar to @command{arc jtag set-aux-reg} but is for core +This command is similar to @command{arc jtag set-aux-reg} but is for core registers. @end deffn @@ -9827,7 +9827,7 @@ therefore it is unsafe to use if that register can be operated by other means. @end deffn @deffn {Command} {arc jtag get-core-reg} regnum -This command is similiar to @command{arc jtag get-aux-reg} but is for core +This command is similar to @command{arc jtag get-aux-reg} but is for core registers. @end deffn |