Redo fespi flash algorithm (#384)

* WIP, rewrite of flash algorithm.

Just put all the flashing logic into the algorithm, instead of using an
intermediate format. This should reduce total data written while
flashing by about 9%, and also makes the code much simpler.

Change-Id: I807e60c8ab4f9f376cceaecdbbd10a2326be1c79

* New algorithm works.

Speeds up Arty flashing another 9%.

wrote 2228224 bytes from file /media/sf_tnewsome/SiFive/arty_images/arty.E21TraceFPGAEvaluationConfig.mcs in 86.784538s (25.074 KiB/s)
verified 2192012 bytes in 6.693336s (319.816 KiB/s)
8.66user 13.03system 1:33.91elapsed 23%CPU (0avgtext+0avgdata 12272maxresident)k

Change-Id: Ie55c5250d667251be141cb32b144bbcf3713fce4

* Fix whitespace.

Change-Id: I338d518fa11a108efb530ffe75a2030619457a0b

* Don't reserve so much stack space.

Also properly check XLEN in riscv_wrapper.S.

Change-Id: Ifa0301f3ea80f648fb8a6d6b6c8bf39f386fe4a6

7 files changed, 417 insertions, 26 deletions

diff --git a/contrib/loaders/flash/fespi/Makefile b/contrib/loaders/flash/fespi/Makefile
index 4d2ab51..f0ee42b 100644
--- a/contrib/loaders/flash/fespi/Makefile
+++ b/contrib/loaders/flash/fespi/Makefile
@@ -2,27 +2,49 @@ BIN2C = ../../../../src/helper/bin2char.sh
 
 CROSS_COMPILE ?= riscv64-unknown-elf-
 
-CC=$(CROSS_COMPILE)gcc
-OBJCOPY=$(CROSS_COMPILE)objcopy
-OBJDUMP=$(CROSS_COMPILE)objdump
+RISCV_CC=$(CROSS_COMPILE)gcc
+RISCV_OBJCOPY=$(CROSS_COMPILE)objcopy
+RISCV_OBJDUMP=$(CROSS_COMPILE)objdump
 
-CFLAGS = -march=rv32i -mabi=ilp32 -x assembler-with-cpp -nostdlib -nostartfiles
+RISCV32_CFLAGS = -march=rv32i -mabi=ilp32 -nostdlib -nostartfiles -Os -fPIC
+RISCV64_CFLAGS = -march=rv64i -mabi=lp64 -nostdlib -nostartfiles -Os -fPIC
 
-all: fespi.inc
+all: riscv32_fespi.inc riscv64_fespi.inc
 
 .PHONY: clean
 
-%.elf: %.S
-	$(CC) $(CFLAGS) $< -o $@
+# .c -> .o
+riscv32_%.o:  riscv_%.c
+	$(RISCV_CC) -c $(RISCV32_CFLAGS) $^ -o $@
 
-%.lst: %.elf
-	$(OBJDUMP) -S $< > $@
+riscv64_%.o:  riscv_%.c
+	$(RISCV_CC) -c $(RISCV64_CFLAGS) $< -o $@
+
+# .S -> .o
+riscv32_%.o:  riscv_%.S
+	$(RISCV_CC) -c $(RISCV32_CFLAGS) $^ -o $@
+
+riscv64_%.o:  riscv_%.S
+	$(RISCV_CC) -c $(RISCV64_CFLAGS) $^ -o $@
+
+# .o -> .elf
+riscv32_%.elf:	riscv32_%.o riscv32_wrapper.o
+	$(RISCV_CC) -T riscv.lds $(RISCV32_CFLAGS) $^ -o $@
 
+riscv64_%.elf:	riscv64_%.o riscv64_wrapper.o
+	$(RISCV_CC) -T riscv.lds $(RISCV64_CFLAGS) $^ -o $@
+
+# .elf -> .bin
 %.bin: %.elf
-	$(OBJCOPY) -Obinary $< $@
+	$(RISCV_OBJCOPY) -Obinary $< $@
 
+# .bin -> .inc
 %.inc: %.bin
 	$(BIN2C) < $< > $@
 
+# utility
+%.lst: %.elf
+	$(RISCV_OBJDUMP) -S $< > $@
+
 clean:
-	-rm -f *.elf *.lst *.bin *.inc
+	-rm -f *.elf *.o *.lst *.bin *.inc
diff --git a/contrib/loaders/flash/fespi/fespi.inc b/contrib/loaders/flash/fespi/fespi.inc
deleted file mode 100644
index 768bdc5..0000000
--- a/contrib/loaders/flash/fespi/fespi.inc
+++ /dev/null
@@ -1,15 +0,0 @@
-/* Autogenerated with ../../../../src/helper/bin2char.sh */
-0x6f,0x00,0xc0,0x01,0x73,0x00,0x10,0x00,0x6f,0x00,0xc0,0x02,0x6f,0x00,0x00,0x05,
-0x6f,0x00,0xc0,0x05,0x6f,0x00,0x00,0x07,0x6f,0x00,0x00,0x0a,0x83,0xc2,0x05,0x00,
-0x93,0x85,0x15,0x00,0x17,0x03,0x00,0x00,0x13,0x03,0xc3,0xfd,0xb3,0x82,0x62,0x00,
-0x67,0x80,0x02,0x00,0x03,0xc3,0x05,0x00,0x93,0x85,0x15,0x00,0x83,0x22,0x85,0x04,
-0xe3,0xce,0x02,0xfe,0x83,0xc2,0x05,0x00,0x23,0x24,0x55,0x04,0x93,0x85,0x15,0x00,
-0x13,0x03,0xf3,0xff,0xe3,0x44,0x60,0xfe,0x6f,0xf0,0x5f,0xfc,0x83,0x22,0x45,0x07,
-0x93,0xf2,0x12,0x00,0xe3,0x8c,0x02,0xfe,0x6f,0xf0,0x5f,0xfb,0x83,0xc2,0x05,0x00,
-0xb3,0x82,0xa2,0x00,0x03,0xc3,0x15,0x00,0x93,0x85,0x25,0x00,0x23,0xa0,0x62,0x00,
-0x6f,0xf0,0xdf,0xf9,0x13,0x06,0x50,0x00,0xef,0x00,0x80,0x01,0x13,0x06,0x00,0x00,
-0xef,0x00,0x00,0x01,0x93,0x72,0x16,0x00,0xe3,0x9a,0x02,0xfe,0x6f,0xf0,0x1f,0xf8,
-0x83,0x22,0x85,0x04,0xe3,0xce,0x02,0xfe,0x23,0x24,0xc5,0x04,0x03,0x26,0xc5,0x04,
-0xe3,0x4e,0x06,0xfe,0x67,0x80,0x00,0x00,0x83,0x22,0x05,0x04,0x13,0x03,0x70,0xff,
-0xb3,0xf2,0x62,0x00,0x03,0xc3,0x05,0x00,0x93,0x85,0x15,0x00,0xb3,0xe2,0x62,0x00,
-0x23,0x20,0x55,0x04,0x6f,0xf0,0x9f,0xf4,
diff --git a/contrib/loaders/flash/fespi/riscv.lds b/contrib/loaders/flash/fespi/riscv.lds
new file mode 100644
index 0000000..524a77c
--- /dev/null
+++ b/contrib/loaders/flash/fespi/riscv.lds
@@ -0,0 +1,12 @@
+OUTPUT_ARCH( "riscv" )
+
+SECTIONS
+{
+  . = 0x80000000;
+  .text :
+  {
+    *(.text.entry)
+    *(.text)
+  }
+  .data : { *(.data) }
+}
diff --git a/contrib/loaders/flash/fespi/riscv32_fespi.inc b/contrib/loaders/flash/fespi/riscv32_fespi.inc
new file mode 100644
index 0000000..9421c69
--- /dev/null
+++ b/contrib/loaders/flash/fespi/riscv32_fespi.inc
@@ -0,0 +1,45 @@
+/* Autogenerated with ../../../../src/helper/bin2char.sh */
+0x17,0x01,0x00,0x00,0x03,0x21,0xc1,0x2a,0xef,0x00,0x00,0x10,0x73,0x00,0x10,0x00,
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+0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,
diff --git a/contrib/loaders/flash/fespi/riscv64_fespi.inc b/contrib/loaders/flash/fespi/riscv64_fespi.inc
new file mode 100644
index 0000000..271c8cc
--- /dev/null
+++ b/contrib/loaders/flash/fespi/riscv64_fespi.inc
@@ -0,0 +1,51 @@
+/* Autogenerated with ../../../../src/helper/bin2char.sh */
+0x17,0x01,0x00,0x00,0x03,0x31,0x81,0x30,0xef,0x00,0x80,0x10,0x73,0x00,0x10,0x00,
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+0x13,0x05,0x04,0x00,0xef,0xf0,0x5f,0xe2,0x93,0xf5,0xf4,0x0f,0x13,0x05,0x04,0x00,
+0xef,0xf0,0x9f,0xe1,0x93,0x0a,0x0a,0x00,0xbb,0x87,0x4a,0x41,0x63,0xec,0x37,0x03,
+0x13,0x05,0x04,0x00,0xef,0xf0,0xdf,0xdd,0x13,0x05,0x04,0x00,0x23,0x2c,0x04,0x00,
+0xef,0xf0,0x5f,0xe2,0x63,0x1a,0x05,0x02,0x93,0x97,0x09,0x02,0x93,0xd7,0x07,0x02,
+0x33,0x0a,0xfa,0x00,0xbb,0x84,0x34,0x01,0x3b,0x09,0x39,0x41,0x93,0x07,0x00,0x00,
+0x6f,0xf0,0x1f,0xf2,0x83,0xc5,0x0a,0x00,0x13,0x05,0x04,0x00,0x93,0x8a,0x1a,0x00,
+0xef,0xf0,0x9f,0xdc,0x6f,0xf0,0x5f,0xfb,0x13,0x0b,0x05,0x00,0x6f,0xf0,0x9f,0xf0,
+0x09,0x53,0x67,0x08,0x00,0x00,0x00,0x00,0x09,0x53,0x67,0x08,0x00,0x00,0x00,0x00,
+0x09,0x53,0x67,0x08,0x00,0x00,0x00,0x00,0x09,0x53,0x67,0x08,0x00,0x00,0x00,0x00,
+0x09,0x53,0x67,0x08,0x00,0x00,0x00,0x00,0x09,0x53,0x67,0x08,0x00,0x00,0x00,0x00,
+0x09,0x53,0x67,0x08,0x00,0x00,0x00,0x00,0x09,0x53,0x67,0x08,0x00,0x00,0x00,0x00,
+0x09,0x53,0x67,0x08,0x00,0x00,0x00,0x00,0x09,0x53,0x67,0x08,0x00,0x00,0x00,0x00,
+0x09,0x53,0x67,0x08,0x00,0x00,0x00,0x00,0x09,0x53,0x67,0x08,0x00,0x00,0x00,0x00,
+0x09,0x53,0x67,0x08,0x00,0x00,0x00,0x00,0x09,0x53,0x67,0x08,0x00,0x00,0x00,0x00,
+0x09,0x53,0x67,0x08,0x00,0x00,0x00,0x00,0x09,0x53,0x67,0x08,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x80,0x00,0x00,0x00,0x00,
+0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
diff --git a/contrib/loaders/flash/fespi/riscv_fespi.c b/contrib/loaders/flash/fespi/riscv_fespi.c
new file mode 100644
index 0000000..79a62a7
--- /dev/null
+++ b/contrib/loaders/flash/fespi/riscv_fespi.c
@@ -0,0 +1,255 @@
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+
+#include "../../../../src/flash/nor/spi.h"
+
+/* Register offsets */
+
+#define FESPI_REG_SCKDIV          0x00
+#define FESPI_REG_SCKMODE         0x04
+#define FESPI_REG_CSID            0x10
+#define FESPI_REG_CSDEF           0x14
+#define FESPI_REG_CSMODE          0x18
+
+#define FESPI_REG_DCSSCK          0x28
+#define FESPI_REG_DSCKCS          0x2a
+#define FESPI_REG_DINTERCS        0x2c
+#define FESPI_REG_DINTERXFR       0x2e
+
+#define FESPI_REG_FMT             0x40
+#define FESPI_REG_TXFIFO          0x48
+#define FESPI_REG_RXFIFO          0x4c
+#define FESPI_REG_TXCTRL          0x50
+#define FESPI_REG_RXCTRL          0x54
+
+#define FESPI_REG_FCTRL           0x60
+#define FESPI_REG_FFMT            0x64
+
+#define FESPI_REG_IE              0x70
+#define FESPI_REG_IP              0x74
+
+/* Fields */
+
+#define FESPI_SCK_POL             0x1
+#define FESPI_SCK_PHA             0x2
+
+#define FESPI_FMT_PROTO(x)        ((x) & 0x3)
+#define FESPI_FMT_ENDIAN(x)       (((x) & 0x1) << 2)
+#define FESPI_FMT_DIR(x)          (((x) & 0x1) << 3)
+#define FESPI_FMT_LEN(x)          (((x) & 0xf) << 16)
+
+/* TXCTRL register */
+#define FESPI_TXWM(x)             ((x) & 0xffff)
+/* RXCTRL register */
+#define FESPI_RXWM(x)             ((x) & 0xffff)
+
+#define FESPI_IP_TXWM             0x1
+#define FESPI_IP_RXWM             0x2
+
+#define FESPI_FCTRL_EN            0x1
+
+#define FESPI_INSN_CMD_EN         0x1
+#define FESPI_INSN_ADDR_LEN(x)    (((x) & 0x7) << 1)
+#define FESPI_INSN_PAD_CNT(x)     (((x) & 0xf) << 4)
+#define FESPI_INSN_CMD_PROTO(x)   (((x) & 0x3) << 8)
+#define FESPI_INSN_ADDR_PROTO(x)  (((x) & 0x3) << 10)
+#define FESPI_INSN_DATA_PROTO(x)  (((x) & 0x3) << 12)
+#define FESPI_INSN_CMD_CODE(x)    (((x) & 0xff) << 16)
+#define FESPI_INSN_PAD_CODE(x)    (((x) & 0xff) << 24)
+
+/* Values */
+
+#define FESPI_CSMODE_AUTO         0
+#define FESPI_CSMODE_HOLD         2
+#define FESPI_CSMODE_OFF          3
+
+#define FESPI_DIR_RX              0
+#define FESPI_DIR_TX              1
+
+#define FESPI_PROTO_S             0
+#define FESPI_PROTO_D             1
+#define FESPI_PROTO_Q             2
+
+#define FESPI_ENDIAN_MSB          0
+#define FESPI_ENDIAN_LSB          1
+/* Timeout in target "loops" */
+#define FESPI_CMD_TIMEOUT         1000
+#define FESPI_PROBE_TIMEOUT       1000
+#define FESPI_MAX_TIMEOUT         30000
+
+enum {
+	ERROR_OK,
+	ERROR_FAIL
+};
+
+static int fespi_txwm_wait(volatile uint32_t *ctrl_base);
+static void fespi_disable_hw_mode(volatile uint32_t *ctrl_base);
+static void fespi_enable_hw_mode(volatile uint32_t *ctrl_base);
+static int fespi_wip(volatile uint32_t *ctrl_base);
+static int slow_fespi_write_buffer(volatile uint32_t *ctrl_base,
+		const uint8_t *buffer, unsigned offset, unsigned len);
+
+int main(volatile uint32_t *ctrl_base, uint32_t page_size,
+		const uint8_t *buffer, unsigned offset, uint32_t count)
+{
+	fespi_txwm_wait(ctrl_base);
+
+	/* Disable Hardware accesses*/
+	fespi_disable_hw_mode(ctrl_base);
+
+	/* poll WIP */
+	int retval = fespi_wip(ctrl_base);
+	if (retval != ERROR_OK)
+		goto err;
+
+	/* Assume page_size is a power of two so we don't need the modulus code. */
+	uint32_t page_offset = offset & (page_size - 1);
+
+	/* central part, aligned words */
+	while (count > 0) {
+		uint32_t cur_count;
+		/* clip block at page boundary */
+		if (page_offset + count > page_size)
+			cur_count = page_size - page_offset;
+		else
+			cur_count = count;
+
+		retval = slow_fespi_write_buffer(ctrl_base, buffer, offset, cur_count);
+		if (retval != ERROR_OK)
+			goto err;
+
+		page_offset = 0;
+		buffer += cur_count;
+		offset += cur_count;
+		count -= cur_count;
+	}
+
+err:
+	/* Switch to HW mode before return to prompt */
+	fespi_enable_hw_mode(ctrl_base);
+
+	return retval;
+}
+
+static uint32_t fespi_read_reg(volatile uint32_t *ctrl_base, unsigned address)
+{
+	return ctrl_base[address / 4];
+}
+
+static void fespi_write_reg(volatile uint32_t *ctrl_base, unsigned address, uint32_t value)
+{
+	ctrl_base[address / 4] = value;
+}
+
+static void fespi_disable_hw_mode(volatile uint32_t *ctrl_base)
+{
+	uint32_t fctrl = fespi_read_reg(ctrl_base, FESPI_REG_FCTRL);
+	fespi_write_reg(ctrl_base, FESPI_REG_FCTRL, fctrl & ~FESPI_FCTRL_EN);
+}
+
+static void fespi_enable_hw_mode(volatile uint32_t *ctrl_base)
+{
+	uint32_t fctrl = fespi_read_reg(ctrl_base, FESPI_REG_FCTRL);
+	fespi_write_reg(ctrl_base, FESPI_REG_FCTRL, fctrl | FESPI_FCTRL_EN);
+}
+
+static int fespi_txwm_wait(volatile uint32_t *ctrl_base)
+{
+	unsigned timeout = 1000;
+
+	while (timeout--) {
+		uint32_t ip = fespi_read_reg(ctrl_base, FESPI_REG_IP);
+		if (ip & FESPI_IP_TXWM)
+			return ERROR_OK;
+	}
+
+	return ERROR_FAIL;
+}
+
+static void fespi_set_dir(volatile uint32_t *ctrl_base, bool dir)
+{
+	uint32_t fmt = fespi_read_reg(ctrl_base, FESPI_REG_FMT);
+	fespi_write_reg(ctrl_base, FESPI_REG_FMT,
+			(fmt & ~(FESPI_FMT_DIR(0xFFFFFFFF))) | FESPI_FMT_DIR(dir));
+}
+
+static int fespi_tx(volatile uint32_t *ctrl_base, uint8_t in)
+{
+	unsigned timeout = 1000;
+
+	while (timeout--) {
+		uint32_t txfifo = fespi_read_reg(ctrl_base, FESPI_REG_TXFIFO);
+		if (!(txfifo >> 31)) {
+			fespi_write_reg(ctrl_base, FESPI_REG_TXFIFO, in);
+			return ERROR_OK;
+		}
+	}
+	return ERROR_FAIL;
+}
+
+static int fespi_rx(volatile uint32_t *ctrl_base, uint8_t *out)
+{
+	unsigned timeout = 1000;
+
+	while (timeout--) {
+		uint32_t value = fespi_read_reg(ctrl_base, FESPI_REG_RXFIFO);
+		if (!(value >> 31)) {
+			if (out)
+				*out = value & 0xff;
+			return ERROR_OK;
+		}
+	}
+
+	return ERROR_FAIL;
+}
+
+static int fespi_wip(volatile uint32_t *ctrl_base)
+{
+	fespi_set_dir(ctrl_base, FESPI_DIR_RX);
+
+	fespi_write_reg(ctrl_base, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD);
+
+	fespi_tx(ctrl_base, SPIFLASH_READ_STATUS);
+	if (fespi_rx(ctrl_base, NULL) != ERROR_OK)
+		return ERROR_FAIL;
+
+	unsigned timeout = 1000;
+	while (timeout--) {
+		fespi_tx(ctrl_base, 0);
+		uint8_t rx;
+		if (fespi_rx(ctrl_base, &rx) != ERROR_OK)
+			return ERROR_FAIL;
+		if ((rx & SPIFLASH_BSY_BIT) == 0) {
+			fespi_write_reg(ctrl_base, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO);
+			fespi_set_dir(ctrl_base, FESPI_DIR_TX);
+			return ERROR_OK;
+		}
+	}
+
+	return ERROR_FAIL;
+}
+
+static int slow_fespi_write_buffer(volatile uint32_t *ctrl_base,
+		const uint8_t *buffer, unsigned offset, unsigned len)
+{
+	fespi_tx(ctrl_base, SPIFLASH_WRITE_ENABLE);
+	fespi_txwm_wait(ctrl_base);
+
+	fespi_write_reg(ctrl_base, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD);
+
+	fespi_tx(ctrl_base, SPIFLASH_PAGE_PROGRAM);
+
+	fespi_tx(ctrl_base, offset >> 16);
+	fespi_tx(ctrl_base, offset >> 8);
+	fespi_tx(ctrl_base, offset);
+
+	for (unsigned i = 0; i < len; i++)
+		fespi_tx(ctrl_base, buffer[i]);
+
+	fespi_txwm_wait(ctrl_base);
+
+	fespi_write_reg(ctrl_base, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO);
+
+	return fespi_wip(ctrl_base);
+}
diff --git a/contrib/loaders/flash/fespi/riscv_wrapper.S b/contrib/loaders/flash/fespi/riscv_wrapper.S
new file mode 100644
index 0000000..caba421
--- /dev/null
+++ b/contrib/loaders/flash/fespi/riscv_wrapper.S
@@ -0,0 +1,21 @@
+#if __riscv_xlen == 64
+# define LREG ld
+# define SREG sd
+# define REGBYTES 8
+#else
+# define LREG lw
+# define SREG sw
+# define REGBYTES 4
+#endif
+
+		.section .text.entry
+		.global _start
+_start:
+		la 		sp, stack_end
+		jal 	main
+		ebreak
+
+		.section .data
+stack:
+		.fill	16, REGBYTES, 0x8675309
+stack_end: