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| author | Tim Newsome <tim@sifive.com> | 2019-09-23 15:51:17 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-09-23 15:51:17 -0700 |
| commit | bf1e201336c8cfbe0a8b3d3667bdff6fe3ce6581 (patch) | |
| tree | 966bace4b4c4b17a9cc502dccf6e1afe814f8f78 /contrib/loaders | |
| parent | c5bb7fb2304c5f4fa62b864185106aaf7c0c1b98 (diff) | |
| download | riscv-openocd-bf1e201336c8cfbe0a8b3d3667bdff6fe3ce6581.zip riscv-openocd-bf1e201336c8cfbe0a8b3d3667bdff6fe3ce6581.tar.gz riscv-openocd-bf1e201336c8cfbe0a8b3d3667bdff6fe3ce6581.tar.bz2 | |
The stack is relative to the program. (#409)
Just like everything else. Fixes flashing on targets that don't have RAM
at 0x80000000.
Change-Id: Ibf423c95ba333660e760d5110f5ce2375c1b762c
Diffstat (limited to 'contrib/loaders')
| -rw-r--r-- | contrib/loaders/flash/fespi/riscv32_fespi.inc | 5 | ||||
| -rw-r--r-- | contrib/loaders/flash/fespi/riscv64_fespi.inc | 4 | ||||
| -rw-r--r-- | contrib/loaders/flash/fespi/riscv_wrapper.S | 5 |
3 files changed, 7 insertions, 7 deletions
diff --git a/contrib/loaders/flash/fespi/riscv32_fespi.inc b/contrib/loaders/flash/fespi/riscv32_fespi.inc index 5e14ff6..338ae35 100644 --- a/contrib/loaders/flash/fespi/riscv32_fespi.inc +++ b/contrib/loaders/flash/fespi/riscv32_fespi.inc @@ -1,5 +1,5 @@ /* Autogenerated with ../../../../src/helper/bin2char.sh */ -0x17,0x01,0x00,0x00,0x03,0x21,0xc1,0x2e,0xef,0x00,0x80,0x10,0x73,0x00,0x10,0x00, +0x17,0x01,0x00,0x00,0x13,0x01,0x81,0x2e,0xef,0x00,0x80,0x10,0x73,0x00,0x10,0x00, 0x93,0x07,0x90,0x3e,0x93,0x87,0xf7,0xff,0x63,0x96,0x07,0x00,0x13,0x05,0x10,0x00, 0x67,0x80,0x00,0x00,0x03,0x27,0x45,0x07,0x13,0x77,0x17,0x00,0xe3,0x04,0x07,0xfe, 0x13,0x05,0x00,0x00,0x67,0x80,0x00,0x00,0x93,0x07,0x90,0x3e,0x93,0x87,0xf7,0xff, @@ -45,5 +45,4 @@ 0x09,0x53,0x67,0x08,0x09,0x53,0x67,0x08,0x09,0x53,0x67,0x08,0x09,0x53,0x67,0x08, 0x09,0x53,0x67,0x08,0x09,0x53,0x67,0x08,0x09,0x53,0x67,0x08,0x09,0x53,0x67,0x08, 0x09,0x53,0x67,0x08,0x09,0x53,0x67,0x08,0x09,0x53,0x67,0x08,0x09,0x53,0x67,0x08, -0x09,0x53,0x67,0x08,0x09,0x53,0x67,0x08,0x00,0x00,0x00,0x00,0xe8,0x02,0x00,0x80, -0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00, +0x09,0x53,0x67,0x08,0x09,0x53,0x67,0x08, diff --git a/contrib/loaders/flash/fespi/riscv64_fespi.inc b/contrib/loaders/flash/fespi/riscv64_fespi.inc index d090641..b8b1d40 100644 --- a/contrib/loaders/flash/fespi/riscv64_fespi.inc +++ b/contrib/loaders/flash/fespi/riscv64_fespi.inc @@ -1,5 +1,5 @@ /* Autogenerated with ../../../../src/helper/bin2char.sh */ -0x17,0x01,0x00,0x00,0x03,0x31,0x81,0x35,0xef,0x00,0x40,0x12,0x73,0x00,0x10,0x00, +0x17,0x01,0x00,0x00,0x13,0x01,0x01,0x35,0xef,0x00,0x40,0x12,0x73,0x00,0x10,0x00, 0x93,0x07,0x90,0x3e,0x9b,0x87,0xf7,0xff,0x63,0x96,0x07,0x00,0x13,0x05,0x10,0x00, 0x67,0x80,0x00,0x00,0x03,0x27,0x45,0x07,0x13,0x77,0x17,0x00,0xe3,0x04,0x07,0xfe, 0x13,0x05,0x00,0x00,0x67,0x80,0x00,0x00,0x93,0x07,0x90,0x3e,0x9b,0x87,0xf7,0xff, @@ -52,5 +52,3 @@ 0x09,0x53,0x67,0x08,0x00,0x00,0x00,0x00,0x09,0x53,0x67,0x08,0x00,0x00,0x00,0x00, 0x09,0x53,0x67,0x08,0x00,0x00,0x00,0x00,0x09,0x53,0x67,0x08,0x00,0x00,0x00,0x00, 0x09,0x53,0x67,0x08,0x00,0x00,0x00,0x00,0x09,0x53,0x67,0x08,0x00,0x00,0x00,0x00, -0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x50,0x03,0x00,0x80,0x00,0x00,0x00,0x00, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, diff --git a/contrib/loaders/flash/fespi/riscv_wrapper.S b/contrib/loaders/flash/fespi/riscv_wrapper.S index b63b48a..c3f11ec 100644 --- a/contrib/loaders/flash/fespi/riscv_wrapper.S +++ b/contrib/loaders/flash/fespi/riscv_wrapper.S @@ -11,7 +11,10 @@ .section .text.entry .global _start _start: - la sp, stack_end + /* Spell out `la sp, stack_end` because otherwise the assembler won't + generate position-independent code. */ +1: auipc sp, %pcrel_hi(stack_end) # load stack_end(hi) + addi sp, sp, %pcrel_lo(1b) # load stack_end(lo) jal flash_fespi ebreak |