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| author | Tim Newsome <tim@sifive.com> | 2018-08-29 14:22:50 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-08-29 14:22:50 -0700 |
| commit | b4b2ec7d2d143146226e7b2f06e1399ee560148d (patch) | |
| tree | 3bd6779f6b72809da344952c36f6310b27a8c902 /contrib/loaders/flash | |
| parent | 074b4fabed1d57ebfc24fcef7cf000906f6d40b8 (diff) | |
| download | riscv-openocd-b4b2ec7d2d143146226e7b2f06e1399ee560148d.zip riscv-openocd-b4b2ec7d2d143146226e7b2f06e1399ee560148d.tar.gz riscv-openocd-b4b2ec7d2d143146226e7b2f06e1399ee560148d.tar.bz2 | |
Add command to expose custom registers (#293)
* Added `riscv expose_custom` command.
Seems to work for reading. I need to do some more testing for writes, as
well as minor cleanup.
Change-Id: I85d5d00897d5da4add4a6643b538be37d31a016f
* Conform to OpenOCD style.
Change-Id: I40a316f06f418d2b63d9e11aea03ef51da8d8faf
* Free all the memory allocated by register init.
Change-Id: I04e35ab54613f99708cee85e41fef989079adefc
* Properly document `riscv expose_custom`.
Change-Id: Id78a02b7a00c161df80f11b521a306e0cf3d7478
Diffstat (limited to 'contrib/loaders/flash')
0 files changed, 0 insertions, 0 deletions