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| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-24 01:27:21 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-24 01:27:21 -0800 |
| commit | bf3abc48f008e0a0c0e42b943481872599463af6 (patch) | |
| tree | 80c502716aaa11bca30689a1938c6385a1a89a24 /TODO | |
| parent | 5eb893ec41c8c6cf6499558b6fed826b65e18a16 (diff) | |
| download | riscv-openocd-bf3abc48f008e0a0c0e42b943481872599463af6.zip riscv-openocd-bf3abc48f008e0a0c0e42b943481872599463af6.tar.gz riscv-openocd-bf3abc48f008e0a0c0e42b943481872599463af6.tar.bz2 | |
ARM11: use standard single step simulation
The previous stuff was needed because the ARM11 code wasn't using
the standard ARM base type and register access ... but now those
mechanisms work, so we can switch out that special-purpose glue.
This should resolve all the "FIXME -- handle Thumb single stepping"
comments too, and properly handle the processor's mode. (Modulo
the issue that this code doesn't yet handle two-byte breakpoints.)
Clarify the comments about the the hardware single stepping. When
we eventually share breakpoint code with Cortex-A8, we can just make
that be the default on cores which support it. We may still want an
override command, not just to facilitate testing but to cope with
"instruction address mismatch" not quite being true single-step.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'TODO')
| -rw-r--r-- | TODO | 3 |
1 files changed, 1 insertions, 2 deletions
@@ -167,8 +167,7 @@ https://lists.berlios.de/pipermail/openocd-development/2009-October/011506.html mdw 0xb80005f0 0x8, mdh 0xb80005f0 0x10, mdb 0xb80005f0 0x20. mdb returns garabage. - implement missing functionality (grep FNC_INFO_NOTIMPLEMENTED ...) - - thumb support is missing: ISTR ARMv6 requires Thumb. - ARM1156 has Thumb2; ARM1136 doesn't. +- Thumb2 single stepping: ARM1156T2 needs simulator support - Cortex A8 support (ML) - add target implementation (ML) - Generic ARM run_algorithm() interface |