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| author | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-04 18:57:31 -0800 |
|---|---|---|
| committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-04 18:57:31 -0800 |
| commit | a0edb8a328ceea23186ab74c941454fb146c9a48 (patch) | |
| tree | 93e1e4f78240e40ba2ae5627055dde51b5b737a5 /NEWS | |
| parent | f4651c869fb0bbe00495a09470af0a934814c92a (diff) | |
| download | riscv-openocd-a0edb8a328ceea23186ab74c941454fb146c9a48.zip riscv-openocd-a0edb8a328ceea23186ab74c941454fb146c9a48.tar.gz riscv-openocd-a0edb8a328ceea23186ab74c941454fb146c9a48.tar.bz2 | |
ARM11: basic watchpoint support
Use the DPM watchpoint support; remove old incomplete stubs.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'NEWS')
| -rw-r--r-- | NEWS | 2 |
1 files changed, 2 insertions, 0 deletions
@@ -24,10 +24,12 @@ Target Layer: - accelerated GDB memory checksum - support "arm regs" command - can access all core modes and registers + - watchpoint support Cortex-A8 - support "arm regs" command - can access all core modes and registers - supports "reset-assert" event (used on OMAP3530) + - watchpoint support Cortex-M3 - Exposed DWT registers like cycle counter |