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| author | Tim Newsome <tim@sifive.com> | 2017-07-14 12:50:11 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-07-14 12:50:11 -0700 |
| commit | f0f1df1061622e564f6984dd0ffeeeb2b612ced2 (patch) | |
| tree | 5c1cb608481e126ee51027ea8f655a1abc0ebcd6 | |
| parent | 43c6fd3b8feeb6a2b762d5dd183cd9e2284c3f32 (diff) | |
| download | riscv-openocd-f0f1df1061622e564f6984dd0ffeeeb2b612ced2.zip riscv-openocd-f0f1df1061622e564f6984dd0ffeeeb2b612ced2.tar.gz riscv-openocd-f0f1df1061622e564f6984dd0ffeeeb2b612ced2.tar.bz2 | |
Fix infinite loop in reset.
| -rw-r--r-- | src/target/riscv/riscv-013.c | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index f82b9bc..7f532f2 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -199,6 +199,14 @@ static void decode_dmi(char *text, unsigned address, unsigned data) uint64_t mask; const char *name; } description[] = { + { DMI_DMCONTROL, DMI_DMCONTROL_HALTREQ, "haltreq" }, + { DMI_DMCONTROL, DMI_DMCONTROL_RESUMEREQ, "resumereq" }, + { DMI_DMCONTROL, DMI_DMCONTROL_HARTRESET, "hartreset" }, + { DMI_DMCONTROL, DMI_DMCONTROL_HASEL, "hasel" }, + { DMI_DMCONTROL, DMI_DMCONTROL_HARTSEL, "hartsel" }, + { DMI_DMCONTROL, DMI_DMCONTROL_NDMRESET, "ndmreset" }, + { DMI_DMCONTROL, DMI_DMCONTROL_DMACTIVE, "dmactive" }, + { DMI_DMSTATUS, DMI_DMSTATUS_ALLRESUMEACK, "allresumeack" }, { DMI_DMSTATUS, DMI_DMSTATUS_ANYRESUMEACK, "anyresumeack" }, { DMI_DMSTATUS, DMI_DMSTATUS_ALLNONEXISTENT, "allnonexistent" }, @@ -1874,7 +1882,16 @@ void riscv013_reset_current_hart(struct target *target) control = set_field(control, DMI_DMCONTROL_NDMRESET, 0); dmi_write(target, DMI_DMCONTROL, control); - while (get_field(dmi_read(target, DMI_DMSTATUS), DMI_DMSTATUS_ALLHALTED) == 0); + for (unsigned i = 0; i < 256; i++) { + uint32_t dmstatus = dmi_read(target, DMI_DMSTATUS); + if (get_field(dmstatus, DMI_DMSTATUS_ALLHALTED)) { + break; + } + if (i == 255) { + LOG_ERROR("Hart didn't halt coming out of reset; dmstatus=0x%x", + dmstatus); + } + } control = set_field(control, DMI_DMCONTROL_HALTREQ, 0); dmi_write(target, DMI_DMCONTROL, control); |