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| author | Tim Newsome <tim@sifive.com> | 2017-07-16 11:16:49 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-07-16 11:48:12 -0700 |
| commit | b032eb1bcc53d43c9cb7a7f04bf2d62ea39af26c (patch) | |
| tree | 226434efa5d2cab02e76b2d7b498962ca1b2f1bd | |
| parent | f0f1df1061622e564f6984dd0ffeeeb2b612ced2 (diff) | |
| download | riscv-openocd-b032eb1bcc53d43c9cb7a7f04bf2d62ea39af26c.zip riscv-openocd-b032eb1bcc53d43c9cb7a7f04bf2d62ea39af26c.tar.gz riscv-openocd-b032eb1bcc53d43c9cb7a7f04bf2d62ea39af26c.tar.bz2 | |
Use a wall clock timeout to complete reset.
| -rw-r--r-- | src/target/riscv/riscv-013.c | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 7f532f2..4b0f71b 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -121,7 +121,8 @@ typedef enum slot { /*** Info about the core being debugged. ***/ -#define WALL_CLOCK_TIMEOUT 2 +#define WALL_CLOCK_TIMEOUT 2 +#define WALL_CLOCK_RESET_TIMEOUT 30 struct trigger { uint64_t address; @@ -1882,14 +1883,17 @@ void riscv013_reset_current_hart(struct target *target) control = set_field(control, DMI_DMCONTROL_NDMRESET, 0); dmi_write(target, DMI_DMCONTROL, control); - for (unsigned i = 0; i < 256; i++) { + time_t start = time(NULL); + + while (1) { uint32_t dmstatus = dmi_read(target, DMI_DMSTATUS); if (get_field(dmstatus, DMI_DMSTATUS_ALLHALTED)) { break; } - if (i == 255) { - LOG_ERROR("Hart didn't halt coming out of reset; dmstatus=0x%x", - dmstatus); + if (time(NULL) - start > WALL_CLOCK_RESET_TIMEOUT) { + LOG_ERROR("Hart didn't halt coming out of reset in %ds; " + "dmstatus=0x%x", WALL_CLOCK_RESET_TIMEOUT, dmstatus); + return; } } |