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| author | Tim Newsome <tim@sifive.com> | 2020-08-18 11:07:34 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-08-18 11:07:34 -0700 |
| commit | c116dc50b221c2fecb54791e9f2f3f6aec38520c (patch) | |
| tree | e5aae542f69c14e4b743d822cc4ff4d421fadc7b | |
| parent | 53ec10b61da5de553c01f92bddf80c076bd49331 (diff) | |
| download | riscv-openocd-c116dc50b221c2fecb54791e9f2f3f6aec38520c.zip riscv-openocd-c116dc50b221c2fecb54791e9f2f3f6aec38520c.tar.gz riscv-openocd-c116dc50b221c2fecb54791e9f2f3f6aec38520c.tar.bz2 | |
Update to version 1.0 of the vector spec. (#505)
Accessing registers on targets that implement 0.9 or earlier will no
longer work. If you need that we can talk about making it a config
option.
Change-Id: I953b639cf9a92ee9b0422e035da57c1d07504237
| -rw-r--r-- | src/target/riscv/riscv-013.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 8025496..6d68287 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1877,7 +1877,7 @@ static int prep_for_vector_access(struct target *target, uint64_t *vtype, if (register_read(target, vl, GDB_REGNO_VL) != ERROR_OK) return ERROR_FAIL; - if (register_write_direct(target, GDB_REGNO_VTYPE, encoded_vsew << 2) != ERROR_OK) + if (register_write_direct(target, GDB_REGNO_VTYPE, encoded_vsew << 3) != ERROR_OK) return ERROR_FAIL; *debug_vl = DIV_ROUND_UP(r->vlenb[r->current_hartid] * 8, riscv_xlen(target)); |