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| author | Tim Newsome <tim@sifive.com> | 2020-07-07 11:55:57 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-07 11:55:57 -0700 |
| commit | 8b929c64970ccb4e1d2ebda7619af24e81b70b3a (patch) | |
| tree | 0625cb5f48f2c67a23fda26d6e9200c51929561b | |
| parent | bbfc666eba84f7133510fa0c5cb1d2d9e7a49bce (diff) | |
| download | riscv-openocd-8b929c64970ccb4e1d2ebda7619af24e81b70b3a.zip riscv-openocd-8b929c64970ccb4e1d2ebda7619af24e81b70b3a.tar.gz riscv-openocd-8b929c64970ccb4e1d2ebda7619af24e81b70b3a.tar.bz2 | |
Triggers with type=0 aren't real. (#496)
Fixes #491.
Change-Id: Id01adcc68d8c7d95f7e86d49d5d2b0c97c9fb1b0
| -rw-r--r-- | src/target/riscv/riscv.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 6640c2d..e213ffa 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -3339,7 +3339,9 @@ int riscv_enumerate_triggers(struct target *target) for (unsigned t = 0; t < RISCV_MAX_TRIGGERS; ++t) { r->trigger_count[hartid] = t; - riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, t); + /* If we can't write tselect, then this hart does not support triggers. */ + if (riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, t) != ERROR_OK) + break; uint64_t tselect_rb; result = riscv_get_register_on_hart(target, &tselect_rb, hartid, GDB_REGNO_TSELECT); @@ -3357,6 +3359,8 @@ int riscv_enumerate_triggers(struct target *target) return result; int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target))); + if (type == 0) + break; switch (type) { case 1: /* On these older cores we don't support software using |