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| author | Marek Vasut <marek.vasut@gmail.com> | 2021-06-12 20:48:51 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2021-06-26 14:39:22 +0100 |
| commit | a38a0afd17d943b8bbc046f5fcfbf150871557a2 (patch) | |
| tree | e39314f69727807ad19ad4d4e1737a153bf4224b | |
| parent | 0ef5144c32ac60ddf3bb005deb3136015e42ae4f (diff) | |
| download | riscv-openocd-a38a0afd17d943b8bbc046f5fcfbf150871557a2.zip riscv-openocd-a38a0afd17d943b8bbc046f5fcfbf150871557a2.tar.gz riscv-openocd-a38a0afd17d943b8bbc046f5fcfbf150871557a2.tar.bz2 | |
tcl/target: Select default boot core on Renesas R-Car Gen2/Gen3
On SMP Renesas R-Car Gen2/Gen3 systems, select the boot core as
the default target using the 'targets' command. This way, the
user can start debugging code running on the boot core without
having to switch to the boot core by explicitly invoking 'targets'
command first, since it is likely the debugged code will run on
the boot core. Note that most of the code is already in place, it
was just not used, so this is more of a fix to make the original
intention work.
Change-Id: I727808adce617c1d9ebd6ffa34f60f5882cdae60
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/6313
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
| -rw-r--r-- | tcl/target/renesas_rcar_gen2.cfg | 3 | ||||
| -rw-r--r-- | tcl/target/renesas_rcar_gen3.cfg | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/tcl/target/renesas_rcar_gen2.cfg b/tcl/target/renesas_rcar_gen2.cfg index 91baa6c..e51b372 100644 --- a/tcl/target/renesas_rcar_gen2.cfg +++ b/tcl/target/renesas_rcar_gen2.cfg @@ -87,12 +87,14 @@ dap create $_DAPNAME -chain-position $_CHIPNAME.cpu set CA15_DBGBASE {0x800B0000 0x800B2000 0x800B4000 0x800B6000} set CA7_DBGBASE {0x800F0000 0x800F2000 0x800F4000 0x800F6000} +set _targets "" set smp_targets "" proc setup_ca {core_name dbgbase num boot} { global _CHIPNAME global _DAPNAME global smp_targets + global _targets for { set _core 0 } { $_core < $num } { incr _core } { set _TARGETNAME $_CHIPNAME.$core_name.$_core set _CTINAME $_TARGETNAME.cti @@ -123,3 +125,4 @@ if { [string equal $_boot_core CA15] } { source [find target/renesas_rcar_reset_common.cfg] eval "target smp $smp_targets" +targets $_targets diff --git a/tcl/target/renesas_rcar_gen3.cfg b/tcl/target/renesas_rcar_gen3.cfg index 5738d37..36e6544 100644 --- a/tcl/target/renesas_rcar_gen3.cfg +++ b/tcl/target/renesas_rcar_gen3.cfg @@ -112,12 +112,14 @@ set CA53_CTIBASE {0x80C20000 0x80D20000 0x80E20000 0x80F20000} set CR7_DBGBASE 0x80910000 set CR7_CTIBASE 0x80918000 +set _targets "" set smp_targets "" proc setup_a5x {core_name dbgbase ctibase num boot} { global _CHIPNAME global _DAPNAME global smp_targets + global _targets for { set _core 0 } { $_core < $num } { incr _core } { set _TARGETNAME $_CHIPNAME.$core_name.$_core set _CTINAME $_TARGETNAME.cti @@ -169,3 +171,4 @@ if { [string equal $_boot_core CA57] } { source [find target/renesas_rcar_reset_common.cfg] eval "target smp $smp_targets" +targets $_targets |