tcl/target: Add support for Renesas R8A779A0 V3U SoC

The V3U SoC is unique in that it now has 8x CA76 and CR52,
while the previous SoCs had CA57/CA53/CR7 . This can still
be handled without too complex modifications to the gen3
configuration file, so add the logic to handle it there.

Change-Id: I7ab33eacc1fd379d369988d3d6690d2e82346c7e
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: http://openocd.zylin.com/6314
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

1 files changed, 41 insertions, 16 deletions

diff --git a/tcl/target/renesas_rcar_gen3.cfg b/tcl/target/renesas_rcar_gen3.cfg
index 36e6544..334d255 100644
--- a/tcl/target/renesas_rcar_gen3.cfg
+++ b/tcl/target/renesas_rcar_gen3.cfg
@@ -7,6 +7,7 @@
 #  H3: Cortex-A57 x 4, Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step)
 # M3W: Cortex-A57 x 2, Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step)
 # M3N: Cortex-A57 x 2,                 Cortex-R7 x 2 (Lock-Step)
+# V3U:                 Cortex-A76 x 8, Cortex-R52 x2 (Lock-Step)
 # V3H:                 Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step)
 # V3M:                 Cortex-A53 x 2, Cortex-R7 x 2 (Lock-Step)
 #  E3:                 Cortex-A53 x 1, Cortex-R7 x 2 (Lock-Step)
@@ -24,6 +25,12 @@ if { [info exists SOC] } {
 	set _soc H3
 }
 
+set _num_ca53 0
+set _num_ca57 0
+set _num_ca76 0
+set _num_cr52 0
+set _num_cr7 0
+
 # Set configuration for each SOC and the default 'BOOT_CORE'
 switch $_soc {
 	H3 {
@@ -75,6 +82,12 @@ switch $_soc {
 		set _num_cr7 0
 		set _boot_core CA53
 	}
+	V3U {
+		set _CHIPNAME r8a779a0
+		set _num_ca76 8
+		set _num_cr52 1
+		set _boot_core CA76
+	}
 	default {
 		error "'$_soc' is invalid!"
 	}
@@ -96,7 +109,7 @@ if { [info exists DAP_TAPID] } {
 	set _DAP_TAPID 0x5ba00477
 }
 
-echo "\t$_soc - $_num_ca57 CA57(s), $_num_ca53 CA53(s), $_num_cr7 CR7(s)"
+echo "\t$_soc - $_num_ca76 CA76(s), $_num_ca57 CA57(s), $_num_ca53 CA53(s), $_num_cr52 CR52(s), $_num_cr7 CR7(s)"
 echo "\tBoot Core - $_boot_core\n"
 
 set _DAPNAME $_CHIPNAME.dap
@@ -105,10 +118,14 @@ set _DAPNAME $_CHIPNAME.dap
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID
 dap create $_DAPNAME -chain-position $_CHIPNAME.cpu
 
+set CA76_DBGBASE {0x81410000 0x81510000 0x81610000 0x81710000 0x81c10000 0x81d10000 0x81e10000 0x81f10000}
+set CA76_CTIBASE {0x81420000 0x81520000 0x81620000 0x81720000 0x81c20000 0x81d20000 0x81e20000 0x81f20000}
 set CA57_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
 set CA57_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
 set CA53_DBGBASE {0x80C10000 0x80D10000 0x80E10000 0x80F10000}
 set CA53_CTIBASE {0x80C20000 0x80D20000 0x80E20000 0x80F20000}
+set CR52_DBGBASE 0x80c10000
+set CR52_CTIBASE 0x80c20000
 set  CR7_DBGBASE 0x80910000
 set  CR7_CTIBASE 0x80918000
 
@@ -137,33 +154,41 @@ proc setup_a5x {core_name dbgbase ctibase num boot} {
 	}
 }
 
-proc setup_cr7 {dbgbase ctibase boot} {
+proc setup_cr7 {core_name dbgbase ctibase num boot} {
 	global _CHIPNAME
 	global _DAPNAME
-	set _TARGETNAME $_CHIPNAME.r7
-	set _CTINAME $_TARGETNAME.cti
-	cti create $_CTINAME -dap $_DAPNAME -ap-num 1 -baseaddr $ctibase
-	set _command "target create $_TARGETNAME cortex_r4 -dap $_DAPNAME \
-		-ap-num 1 -dbgbase $dbgbase"
-	if { $boot == 1 } {
-		set _targets "$_TARGETNAME"
-	} else {
-		set _command "$_command -defer-examine"
+	for { set _core 0 } { $_core < $num } { incr _core } {
+		set _TARGETNAME $_CHIPNAME.$core_name
+		set _CTINAME $_TARGETNAME.cti
+		cti create $_CTINAME -dap $_DAPNAME -ap-num 1 -baseaddr $ctibase
+		set _command "target create $_TARGETNAME cortex_r4 -dap $_DAPNAME \
+			-ap-num 1 -dbgbase $dbgbase"
+		if { $boot == 1 } {
+			set _targets "$_TARGETNAME"
+		} else {
+			set _command "$_command -defer-examine"
+		}
+		eval $_command
 	}
-	eval $_command
 }
 
 # Organize target list based on the boot core
-if { [string equal $_boot_core CA57] } {
+if { [string equal $_boot_core CA76] } {
+	setup_a5x a76 $CA76_DBGBASE $CA76_CTIBASE $_num_ca76 1
+	setup_cr7 r52 $CR52_DBGBASE $CR52_CTIBASE $_num_cr52 0
+} elseif { [string equal $_boot_core CA57] } {
 	setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 1
 	setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0
-	setup_cr7 $CR7_DBGBASE $CR7_CTIBASE 0
+	setup_cr7 r7  $CR7_DBGBASE  $CR7_CTIBASE  $_num_cr7  0
 } elseif { [string equal $_boot_core CA53] } {
 	setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 1
 	setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0
-	setup_cr7 $CR7_DBGBASE $CR7_CTIBASE 0
+	setup_cr7 r7  $CR7_DBGBASE  $CR7_CTIBASE  $_num_cr7  0
+} elseif { [string equal $_boot_core CR52] } {
+	setup_cr7 r52 $CR52_DBGBASE $CR52_CTIBASE $_num_cr52 1
+	setup_a5x a76 $CA76_DBGBASE $CA76_CTIBASE $_num_ca76 0
 } else {
-	setup_cr7 $CR7_DBGBASE $CR7_CTIBASE 1
+	setup_cr7 r7  $CR7_DBGBASE  $CR7_CTIBASE  $_num_cr7  1
 	setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0
 	setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0
 }