diff options
| author | Olivier DANET <odanet@caramail.com> | 2021-05-17 14:47:14 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2021-05-22 10:12:01 +0100 |
| commit | 4e872a797f81595d5de790138bdec62f2bf175f0 (patch) | |
| tree | 82d5e8b2e822bb8cd9b145e823fb0328528c7cc4 | |
| parent | 036de3b48217e9c0b5ec0bbf6638e9cad6cae517 (diff) | |
| download | riscv-openocd-4e872a797f81595d5de790138bdec62f2bf175f0.zip riscv-openocd-4e872a797f81595d5de790138bdec62f2bf175f0.tar.gz riscv-openocd-4e872a797f81595d5de790138bdec62f2bf175f0.tar.bz2 | |
target/zynqmp : Add AXI AP access port
The Xilinx Zynq UltraScale+ SoC have an "AXI-AP" access port for direct memory accesses without halting CPUs.
Change-Id: I6303331c217795657575de4759444938e775dee1
Signed-off-by: Olivier DANET <odanet@caramail.com>
Reviewed-on: http://openocd.zylin.com/6263
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
| -rw-r--r-- | tcl/target/xilinx_zynqmp.cfg | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tcl/target/xilinx_zynqmp.cfg b/tcl/target/xilinx_zynqmp.cfg index b21603f..e66289a 100644 --- a/tcl/target/xilinx_zynqmp.cfg +++ b/tcl/target/xilinx_zynqmp.cfg @@ -92,6 +92,8 @@ for { set _core 0 } { $_core < $_cores } { incr _core } { eval $_command } +target create uscale.axi mem_ap -dap uscale.dap -ap-num 0 + eval $_smp_command targets $_TARGETNAME.0 |