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author | Tim Newsome <tim@sifive.com> | 2018-06-20 14:52:38 -0700 |
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committer | Tim Newsome <tim@sifive.com> | 2018-06-20 14:52:38 -0700 |
commit | 6c59fb8df4a511b05f23d9be9e1854205a401206 (patch) | |
tree | e2876c53c671a6f44aee367d1099766dc165495d | |
parent | 5d9f48640461fbac5c30958f63a01e666ee64dd4 (diff) | |
download | riscv-openocd-6c59fb8df4a511b05f23d9be9e1854205a401206.zip riscv-openocd-6c59fb8df4a511b05f23d9be9e1854205a401206.tar.gz riscv-openocd-6c59fb8df4a511b05f23d9be9e1854205a401206.tar.bz2 |
Explain why reg_cache_values isn't per-hart.
Change-Id: Ie67e43bf89fdc68b4b2c12f37fa8a3ec3e6088ef
-rw-r--r-- | src/target/riscv/riscv.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h index 4fb0f77..a5b324d 100644 --- a/src/target/riscv/riscv.h +++ b/src/target/riscv/riscv.h @@ -58,7 +58,9 @@ typedef struct { uint64_t saved_registers[RISCV_MAX_HARTS][RISCV_MAX_REGISTERS]; bool valid_saved_registers[RISCV_MAX_HARTS][RISCV_MAX_REGISTERS]; - /* The register cache points into here. */ + /* OpenOCD's register cache points into here. This is not per-hart because + * we just invalidate the entire cache when we change which hart is + * selected. */ uint64_t reg_cache_values[RISCV_MAX_REGISTERS]; /* Single buffer that contains all register names, instead of calling |