diff options
| author | Jonathan McDowell <noodles@earth.li> | 2019-01-14 10:51:37 +0000 |
|---|---|---|
| committer | Matthias Welwarsky <matthias@welwarsky.de> | 2019-01-23 15:26:48 +0000 |
| commit | d2fb461621dc97a611e7bb44a2a64e1efe300875 (patch) | |
| tree | b2ebaabe29efe6ab9d95bbac81e580a25d6f4eed | |
| parent | 45b4998e9369029d48c1f33fbccb1a525793cd46 (diff) | |
| download | riscv-openocd-d2fb461621dc97a611e7bb44a2a64e1efe300875.zip riscv-openocd-d2fb461621dc97a611e7bb44a2a64e1efe300875.tar.gz riscv-openocd-d2fb461621dc97a611e7bb44a2a64e1efe300875.tar.bz2 | |
Correct ZynqMP configuration to be appropriately named
The xilinx_ultrascale.cfg target is actually the configuration for a
ZynqMP, which is a combination of an UltraScale+ FPGA core and a quad
core A53. Update the filename/comments to reflect this, and include
the tap IDs for all known FPGA cores for this part.
Change-Id: I70dfcc99861a482b83b6a795e83021d9cf1fe047
Signed-off-by: Jonathan McDowell <noodles@earth.li>
Reviewed-on: http://openocd.zylin.com/4850
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
| -rw-r--r-- | tcl/board/avnet_ultrazed-eg.cfg | 4 | ||||
| -rw-r--r-- | tcl/target/xilinx_zynqmp.cfg (renamed from tcl/target/xilinx_ultrascale.cfg) | 23 |
2 files changed, 19 insertions, 8 deletions
diff --git a/tcl/board/avnet_ultrazed-eg.cfg b/tcl/board/avnet_ultrazed-eg.cfg index a0ac5c6..9879bfc 100644 --- a/tcl/board/avnet_ultrazed-eg.cfg +++ b/tcl/board/avnet_ultrazed-eg.cfg @@ -1,6 +1,6 @@ # # AVNET UltraZED EG StarterKit -# UlraScale-EG plus IO Carrier with on-board digilent smt2 +# ZynqMP UlraScale-EG plus IO Carrier with on-board digilent smt2 # source [find interface/ftdi/digilent_jtag_smt2_nc.cfg] # jtag transport only @@ -13,4 +13,4 @@ adapter_khz 1000 set CHIPNAME uscale -source [find target/xilinx_ultrascale.cfg] +source [find target/xilinx_zynqmp.cfg] diff --git a/tcl/target/xilinx_ultrascale.cfg b/tcl/target/xilinx_zynqmp.cfg index 9056c97..9be781c 100644 --- a/tcl/target/xilinx_ultrascale.cfg +++ b/tcl/target/xilinx_zynqmp.cfg @@ -1,6 +1,6 @@ # # target configuration for -# Xilinx UltraScale+ +# Xilinx ZynqMP (UltraScale+ / A53) # if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME @@ -9,7 +9,7 @@ if { [info exists CHIPNAME] } { } # -# DAP tap +# DAP tap (Quard core A53) # if { [info exists DAP_TAPID] } { set _DAP_TAPID $DAP_TAPID @@ -21,18 +21,29 @@ jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DA dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap # -# PS tap +# PS tap (UltraScale+) # if { [info exists PS_TAPID] } { set _PS_TAPID $PS_TAPID + jtag newtap $_CHIPNAME ps -irlen 12 -ircapture 0x1 -irmask 0x03 -expected-id $_PS_TAPID } else { - set _PS_TAPID 0x04710093 + # FPGA Programmable logic. Values take from Table 39-1 in UG1085: + jtag newtap $_CHIPNAME ps -irlen 12 -ircapture 0x1 -irmask 0x03 -ignore-version \ + -expected-id 0x04711093 \ + -expected-id 0x04710093 \ + -expected-id 0x04721093 \ + -expected-id 0x04720093 \ + -expected-id 0x04739093 \ + -expected-id 0x04730093 \ + -expected-id 0x04738093 \ + -expected-id 0x04740093 \ + -expected-id 0x04750093 \ + -expected-id 0x04759093 \ + -expected-id 0x04758093 } set jtag_configured 0 -jtag newtap $_CHIPNAME ps -irlen 12 -ircapture 0x1 -irmask 0x03 -expected-id $_PS_TAPID - jtag configure $_CHIPNAME.ps -event setup { global _CHIPNAME global jtag_configured |