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| author | Marc Schink <openocd-dev@marcschink.de> | 2019-02-26 14:10:09 +0100 |
|---|---|---|
| committer | Tomas Vanek <vanekt@fbl.cz> | 2019-03-06 16:19:28 +0000 |
| commit | c69da2eb0c118dbcfcc26090355fa23818cec61e (patch) | |
| tree | 2fb066ae126dc4e442808bceb76213281007de07 | |
| parent | ffd8e2b630600703805c6500f92da8775aa88d10 (diff) | |
| download | riscv-openocd-c69da2eb0c118dbcfcc26090355fa23818cec61e.zip riscv-openocd-c69da2eb0c118dbcfcc26090355fa23818cec61e.tar.gz riscv-openocd-c69da2eb0c118dbcfcc26090355fa23818cec61e.tar.bz2 | |
target/lakemont: Use 'bool' data type
Change-Id: I9baaf617c2bfabd07ac3ca195e486893d7950398
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4969
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
| -rw-r--r-- | src/target/lakemont.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/src/target/lakemont.c b/src/target/lakemont.c index b81213e..31882b8 100644 --- a/src/target/lakemont.c +++ b/src/target/lakemont.c @@ -322,8 +322,8 @@ static int restore_context(struct target *t) } for (i = 0; i < (x86_32->cache->num_regs); i++) { - x86_32->cache->reg_list[i].dirty = 0; - x86_32->cache->reg_list[i].valid = 0; + x86_32->cache->reg_list[i].dirty = false; + x86_32->cache->reg_list[i].valid = false; } return err; } @@ -357,8 +357,8 @@ static int lakemont_set_core_reg(struct reg *reg, uint8_t *buf) if (check_not_halted(t)) return ERROR_TARGET_NOT_HALTED; buf_set_u32(reg->value, 0, 32, value); - reg->dirty = 1; - reg->valid = 1; + reg->dirty = true; + reg->valid = true; return ERROR_OK; } @@ -405,8 +405,8 @@ struct reg_cache *lakemont_build_reg_cache(struct target *t) reg_list[i].name = regs[i].name; reg_list[i].size = 32; reg_list[i].value = calloc(1, 4); - reg_list[i].dirty = 0; - reg_list[i].valid = 0; + reg_list[i].dirty = false; + reg_list[i].valid = false; reg_list[i].type = &lakemont_reg_type; reg_list[i].arch_info = &arch_info[i]; @@ -667,8 +667,8 @@ static int read_hw_reg(struct target *t, int reg, uint32_t *regval, uint8_t cach *regval = buf_get_u32(scan.out, 0, 32); if (cache) { buf_set_u32(x86_32->cache->reg_list[reg].value, 0, 32, *regval); - x86_32->cache->reg_list[reg].valid = 1; - x86_32->cache->reg_list[reg].dirty = 0; + x86_32->cache->reg_list[reg].valid = true; + x86_32->cache->reg_list[reg].dirty = false; } LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=0x%08" PRIx32, x86_32->cache->reg_list[reg].name, @@ -709,8 +709,8 @@ static int write_hw_reg(struct target *t, int reg, uint32_t regval, uint8_t cach /* we are writing from the cache so ensure we reset flags */ if (cache) { - x86_32->cache->reg_list[reg].dirty = 0; - x86_32->cache->reg_list[reg].valid = 0; + x86_32->cache->reg_list[reg].dirty = false; + x86_32->cache->reg_list[reg].valid = false; } return ERROR_OK; } @@ -947,8 +947,8 @@ int lakemont_poll(struct target *t) * breakpoint instruction. This needs to be corrected. */ buf_set_u32(x86_32->cache->reg_list[EIP].value, 0, 32, eip-1); - x86_32->cache->reg_list[EIP].dirty = 1; - x86_32->cache->reg_list[EIP].valid = 1; + x86_32->cache->reg_list[EIP].dirty = true; + x86_32->cache->reg_list[EIP].valid = true; LOG_USER("hit software breakpoint at 0x%08" PRIx32, eip-1); } else { /* it's not a hardware breakpoint (checked already in DR6 state) |