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| author | Marc Schink <openocd-dev@marcschink.de> | 2019-02-26 14:11:15 +0100 |
|---|---|---|
| committer | Tomas Vanek <vanekt@fbl.cz> | 2019-03-06 16:20:32 +0000 |
| commit | 6431a85b0ad3a39895be780053d589a1bf1b88c2 (patch) | |
| tree | 868e7fa539ba1157add440f53aa68d94fdbd81e5 | |
| parent | c69da2eb0c118dbcfcc26090355fa23818cec61e (diff) | |
| download | riscv-openocd-6431a85b0ad3a39895be780053d589a1bf1b88c2.zip riscv-openocd-6431a85b0ad3a39895be780053d589a1bf1b88c2.tar.gz riscv-openocd-6431a85b0ad3a39895be780053d589a1bf1b88c2.tar.bz2 | |
target/openrisc/or1k: Use 'bool' data type
Change-Id: I6393bb8503d64947a1f2349e1d14c1552cabf927
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4971
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
| -rw-r--r-- | src/target/openrisc/or1k.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/target/openrisc/or1k.c b/src/target/openrisc/or1k.c index bcb648c..34b1b07 100644 --- a/src/target/openrisc/or1k.c +++ b/src/target/openrisc/or1k.c @@ -424,8 +424,8 @@ static int or1k_read_core_reg(struct target *target, int num) reg_value = or1k->core_regs[num]; buf_set_u32(or1k->core_cache->reg_list[num].value, 0, 32, reg_value); LOG_DEBUG("Read core reg %i value 0x%08" PRIx32, num , reg_value); - or1k->core_cache->reg_list[num].valid = 1; - or1k->core_cache->reg_list[num].dirty = 0; + or1k->core_cache->reg_list[num].valid = true; + or1k->core_cache->reg_list[num].dirty = false; } else { /* This is an spr, always read value from HW */ int retval = du_core->or1k_jtag_read_cpu(&or1k->jtag, @@ -453,8 +453,8 @@ static int or1k_write_core_reg(struct target *target, int num) uint32_t reg_value = buf_get_u32(or1k->core_cache->reg_list[num].value, 0, 32); or1k->core_regs[num] = reg_value; LOG_DEBUG("Write core reg %i value 0x%08" PRIx32, num , reg_value); - or1k->core_cache->reg_list[num].valid = 1; - or1k->core_cache->reg_list[num].dirty = 0; + or1k->core_cache->reg_list[num].valid = true; + or1k->core_cache->reg_list[num].dirty = false; return ERROR_OK; } @@ -487,8 +487,8 @@ static int or1k_set_core_reg(struct reg *reg, uint8_t *buf) if (or1k_reg->list_num < OR1KNUMCOREREGS) { buf_set_u32(reg->value, 0, 32, value); - reg->dirty = 1; - reg->valid = 1; + reg->dirty = true; + reg->valid = true; } else { /* This is an spr, write it to the HW */ int retval = du_core->or1k_jtag_write_cpu(&or1k->jtag, @@ -541,8 +541,8 @@ static struct reg_cache *or1k_build_reg_cache(struct target *target) reg_list[i].group = or1k_core_reg_list_arch_info[i].group; reg_list[i].size = 32; reg_list[i].value = calloc(1, 4); - reg_list[i].dirty = 0; - reg_list[i].valid = 0; + reg_list[i].dirty = false; + reg_list[i].valid = false; reg_list[i].type = &or1k_reg_type; reg_list[i].arch_info = &arch_info[i]; reg_list[i].number = i; |