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author | Tim Newsome <tim@sifive.com> | 2020-03-27 11:21:02 -0700 |
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committer | GitHub <noreply@github.com> | 2020-03-27 11:21:02 -0700 |
commit | cbb15587dc782ac8ade7ae252e7b760cfba4a178 (patch) | |
tree | 935eb758a34f7ddcb02990cc68a5a4d571d81e03 | |
parent | 3967f48843bbfb69e7ea039aaf3727cced8e0458 (diff) | |
download | riscv-openocd-cbb15587dc782ac8ade7ae252e7b760cfba4a178.zip riscv-openocd-cbb15587dc782ac8ade7ae252e7b760cfba4a178.tar.gz riscv-openocd-cbb15587dc782ac8ade7ae252e7b760cfba4a178.tar.bz2 |
Document default values for some config options. (#461)
Change-Id: I4373b9487ea11664d3a6ea7ea10e99ea6d337232
-rw-r--r-- | doc/openocd.texi | 12 | ||||
-rw-r--r-- | src/target/riscv/riscv.c | 7 |
2 files changed, 10 insertions, 9 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index 0e92a9d..2624477 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -9468,20 +9468,20 @@ This is used to access 64-bit floating point registers on 32-bit targets. @end deffn @deffn Command {riscv set_prefer_sba} on|off -When on, prefer to use System Bus Access to access memory. When off, prefer to -use the Program Buffer to access memory. +When on, prefer to use System Bus Access to access memory. When off (default), +prefer to use the Program Buffer to access memory. @end deffn @deffn Command {riscv set_enable_virtual} on|off When on, memory accesses are performed on physical or virtual memory depending -on the current system configuration. When off, all memory accessses are performed +on the current system configuration. When off (default), all memory accessses are performed on physical memory. @end deffn @deffn Command {riscv set_enable_virt2phys} on|off -When on, memory accesses are performed on physical or virtual memory depending -on the current satp configuration. When off, all memory accessses are performed -on physical memory. +When on (default), memory accesses are performed on physical or virtual memory +depending on the current satp configuration. When off, all memory accessses are +performed on physical memory. @end deffn @deffn Command {riscv resume_order} normal|reversed diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 61aaa5d..0adc299 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -2541,7 +2541,7 @@ static const struct command_registration riscv_exec_command_handlers[] = { .mode = COMMAND_ANY, .usage = "riscv set_prefer_sba on|off", .help = "When on, prefer to use System Bus Access to access memory. " - "When off, prefer to use the Program Buffer to access memory." + "When off (default), prefer to use the Program Buffer to access memory." }, { .name = "set_enable_virtual", @@ -2550,7 +2550,7 @@ static const struct command_registration riscv_exec_command_handlers[] = { .usage = "riscv set_enable_virtual on|off", .help = "When on, memory accesses are performed on physical or virtual " "memory depending on the current system configuration. " - "When off, all memory accessses are performed on physical memory." + "When off (default), all memory accessses are performed on physical memory." }, { .name = "expose_csrs", @@ -2653,7 +2653,8 @@ static const struct command_registration riscv_exec_command_handlers[] = { .handler = riscv_set_enable_virt2phys, .mode = COMMAND_ANY, .usage = "riscv set_enable_virt2phys on|off", - .help = "Enable translation from virtual address to physical address." + .help = "When on (default), enable translation from virtual address to " + "physical address." }, { .name = "set_ebreakm", |