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| author | Tim Newsome <tim@sifive.com> | 2020-03-26 09:08:56 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-26 09:08:56 -0700 |
| commit | 5b2426a4b2c3d0eb244bb8ec276ef24228e9e31d (patch) | |
| tree | 187bc82c115b244bfee14ba6d7d2880616651b40 | |
| parent | 548790fefc5da04a2a60d6fb54f765c7bf959e42 (diff) | |
| download | riscv-openocd-5b2426a4b2c3d0eb244bb8ec276ef24228e9e31d.zip riscv-openocd-5b2426a4b2c3d0eb244bb8ec276ef24228e9e31d.tar.gz riscv-openocd-5b2426a4b2c3d0eb244bb8ec276ef24228e9e31d.tar.bz2 | |
Deal with vlenb being unreadable. (#458)
Instead of exiting during examine(), spit out a warning, and don't
expose the vector data registers. We do provide access to the vector
CSRs, because maybe they do work? It's just that we have no idea what
the size of the data registers is.
Change-Id: I6e9ffeb242e2e22fc62cb1b50782c2efb4ace0bd
| -rw-r--r-- | src/target/riscv/riscv-013.c | 8 | ||||
| -rw-r--r-- | src/target/riscv/riscv.c | 2 | ||||
| -rw-r--r-- | src/target/riscv/riscv.h | 1 |
3 files changed, 8 insertions, 3 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 487ed50..662db7a 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1541,8 +1541,12 @@ static int discover_vlenb(struct target *target, int hartid) RISCV_INFO(r); riscv_reg_t vlenb; - if (register_read(target, &vlenb, GDB_REGNO_VLENB) != ERROR_OK) - return ERROR_FAIL; + if (register_read(target, &vlenb, GDB_REGNO_VLENB) != ERROR_OK) { + LOG_WARNING("Couldn't read vlenb for %s; vector register access won't " + "work.", target_name(target)); + r->vlenb[hartid] = 0; + return ERROR_OK; + } r->vlenb[hartid] = vlenb; LOG_INFO("hart %d: Vector support with vlenb=%d", hartid, r->vlenb[hartid]); diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 929746f..61aaa5d 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -4023,7 +4023,7 @@ int riscv_init_registers(struct target *target) } else if (number >= GDB_REGNO_V0 && number <= GDB_REGNO_V31) { r->caller_save = false; - r->exist = riscv_supports_extension(target, hartid, 'V'); + r->exist = riscv_supports_extension(target, hartid, 'V') && info->vlenb[hartid]; r->size = info->vlenb[hartid] * 8; sprintf(reg_name, "v%d", number - GDB_REGNO_V0); r->group = "vector"; diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h index 7233579..ae8bdde 100644 --- a/src/target/riscv/riscv.h +++ b/src/target/riscv/riscv.h @@ -75,6 +75,7 @@ typedef struct { /* It's possible that each core has a different supported ISA set. */ int xlen[RISCV_MAX_HARTS]; riscv_reg_t misa[RISCV_MAX_HARTS]; + /* Cached value of vlenb. 0 if vlenb is not readable for some reason. */ unsigned vlenb[RISCV_MAX_HARTS]; /* The number of triggers per hart. */ |