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| author | Tim Newsome <tim@sifive.com> | 2017-06-16 09:28:08 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-06-16 14:02:25 -0700 |
| commit | fd81f7fcac9b62d9c40d690d00e43928e8731b79 (patch) | |
| tree | 72c48ce8b705ee30cda94568757e50f8accf0323 | |
| parent | 851849a29582f789d886ed30a9f0f60bb1cfd52e (diff) | |
| download | riscv-openocd-fd81f7fcac9b62d9c40d690d00e43928e8731b79.zip riscv-openocd-fd81f7fcac9b62d9c40d690d00e43928e8731b79.tar.gz riscv-openocd-fd81f7fcac9b62d9c40d690d00e43928e8731b79.tar.bz2 | |
Fix comment.
| -rw-r--r-- | src/target/riscv/riscv-013.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index d529726..abad446 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1895,7 +1895,7 @@ static void riscv013_step_or_resume_current_hart(struct target *target, bool ste if (riscv_program_exec(&program, target) != ERROR_OK) abort(); - /* Issue the halt command, and then wait for the current hart to halt. */ + /* Issue the resume command, and then wait for the current hart to resume. */ uint32_t dmcontrol = dmi_read(target, DMI_DMCONTROL); dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_RESUMEREQ, 1); dmi_write(target, DMI_DMCONTROL, dmcontrol); |