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| author | bluew <bluewww@users.noreply.github.com> | 2019-12-06 02:22:12 +0100 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2019-12-05 17:22:12 -0800 |
| commit | aec5cca15b41d778fb85e95b38a9a552438fec6a (patch) | |
| tree | a55a45e3cbefce6080fd231532c6128f2c7dff5e | |
| parent | 780d8e4d3eb57b7d68d602ed480f21d6d9ebc127 (diff) | |
| download | riscv-openocd-aec5cca15b41d778fb85e95b38a9a552438fec6a.zip riscv-openocd-aec5cca15b41d778fb85e95b38a9a552438fec6a.tar.gz riscv-openocd-aec5cca15b41d778fb85e95b38a9a552438fec6a.tar.bz2 | |
Increase maximum number of harts (#429)
OpenOCD can't deal with systems that have more than 32 harts.
| -rw-r--r-- | src/target/riscv/riscv.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h index 9d6e399..afea3ee 100644 --- a/src/target/riscv/riscv.h +++ b/src/target/riscv/riscv.h @@ -9,7 +9,7 @@ struct riscv_program; #include "jtag/jtag.h" /* The register cache is statically allocated. */ -#define RISCV_MAX_HARTS 32 +#define RISCV_MAX_HARTS 1024 #define RISCV_MAX_REGISTERS 5000 #define RISCV_MAX_TRIGGERS 32 #define RISCV_MAX_HWBPS 16 |