tcl/stm32l5x|u5x: refactor common tcl code

both stm32l5x and stm32u5x configs are almost identical except
clock config.

while at there rename target procs to avoid issues with JTAG daisy
chaining.

Change-Id: Ibbb1dfeb91a7f8d5d45744cf57dca2877f60e0c5
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6596
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins

3 files changed, 164 insertions, 315 deletions

diff --git a/tcl/target/stm32l5x.cfg b/tcl/target/stm32l5x.cfg
index 0616df1..c43b699 100644
--- a/tcl/target/stm32l5x.cfg
+++ b/tcl/target/stm32l5x.cfg
@@ -1,10 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 # script for stm32l5x family
+# stm32l5x devices support both JTAG and SWD transports.
 
-#
-# stm32l5 devices support both JTAG and SWD transports.
-#
 source [find target/swj-dp.tcl]
 source [find mem_helper.tcl]
 
@@ -14,78 +12,10 @@ if { [info exists CHIPNAME] } {
 	set _CHIPNAME stm32l5x
 }
 
-set _ENDIAN little
+source [find target/stm32x5x_common.cfg]
 
-# Work-area is a space in RAM used for flash programming
-# By default use 64kB
-if { [info exists WORKAREASIZE] } {
-	set _WORKAREASIZE $WORKAREASIZE
-} else {
-	set _WORKAREASIZE 0x10000
-}
-
-#jtag scan chain
-if { [info exists CPUTAPID] } {
-	set _CPUTAPID $CPUTAPID
-} else {
-	if { [using_jtag] } {
-		# See STM Document RM0438
-		# RM0438 Rev5, Section 52.2.8 JTAG debug port - Table 425. JTAG-DP data registers
-		# Corresponds to Cortex®-M33 JTAG debug port ID code
-		set _CPUTAPID 0x0ba04477
-	} {
-		# SWD IDCODE (single drop, arm)
-		set _CPUTAPID 0x0be12477
-	}
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
-
-if {[using_jtag]} {
-	jtag newtap $_CHIPNAME bs -irlen 5
-}
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
-
-# use non-secure RAM by default
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-# create sec/ns flash and otp memories (sizes will be probed)
-flash bank $_CHIPNAME.flash_ns      stm32l4x 0x08000000 0 0 0 $_TARGETNAME
-flash bank $_CHIPNAME.flash_alias_s stm32l4x 0x0C000000 0 0 0 $_TARGETNAME
-flash bank $_CHIPNAME.otp           stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME
-
-# Common knowledges tells JTAG speed should be <= F_CPU/6.
-# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
-# the safe side.
-#
-# Note that there is a pretty wide band where things are
-# more or less stable, see http://openocd.zylin.com/#/c/3366/
-adapter speed 500
-
-adapter srst delay 100
-if {[using_jtag]} {
-	jtag_ntrst_delay 100
-}
-
-reset_config srst_nogate
-
-if {![using_hla]} {
-	# if srst is not fitted use SYSRESETREQ to
-	# perform a soft reset
-	cortex_m reset_config sysresetreq
-}
-
-proc is_secure {} {
-	# read Debug Security Control and Status Regsiter (DSCSR) and check CDS (bit 16)
-	set DSCSR [mrw 0xE000EE08]
-	return [expr {($DSCSR & (1 << 16)) != 0}]
-}
-
-proc clock_config_110_mhz {} {
-	set offset [expr {[is_secure] ? 0x10000000 : 0}]
+proc stm32l5x_clock_config {} {
+	set offset [expr {[stm32x5x_is_secure] ? 0x10000000 : 0}]
 	# MCU clock is MSI (4MHz) after reset, set MCU freq at 110 MHz with PLL
 	# RCC_APB1ENR1 = PWREN
 	mww [expr {0x40021058 + $offset}] 0x10000000
@@ -111,90 +41,8 @@ proc clock_config_110_mhz {} {
 	while {([mrw [expr {0x40021008 + $offset}]] & 0x0C) != 0x0C} {}
 }
 
-proc ahb_ap_non_secure_access {} {
-	# SPROT=1=Non Secure access, Priv=1
-	[[target current] cget -dap] apcsw 0x4B000000 0x4F000000
-}
-
-proc ahb_ap_secure_access {} {
-	# SPROT=0=Secure access, Priv=1
-	[[target current] cget -dap] apcsw 0x0B000000 0x4F000000
-}
-
 $_TARGETNAME configure -event reset-init {
-	clock_config_110_mhz
+	stm32l5x_clock_config
 	# Boost JTAG frequency
 	adapter speed 4000
 }
-
-$_TARGETNAME configure -event reset-start {
-	# Reset clock is MSI (4 MHz)
-	adapter speed 480
-}
-
-$_TARGETNAME configure -event examine-end {
-	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
-	mmw 0xE0044004 0x00000006 0
-
-	# Stop watchdog counters during halt
-	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
-	mmw 0xE0044008 0x00001800 0
-}
-
-$_TARGETNAME configure -event halted {
-	set secure [is_secure]
-
-	if {$secure} {
-		set secure_str "Secure"
-		ahb_ap_secure_access
-	} else {
-		set secure_str "Non-Secure"
-		ahb_ap_non_secure_access
-	}
-
-	# print the secure state only when it changes
-	set _TARGETNAME [target current]
-	global $_TARGETNAME.secure
-
-	if {![info exists $_TARGETNAME.secure] || $secure != [set $_TARGETNAME.secure]} {
-		echo "CPU in $secure_str state"
-		# update saved security state
-		set $_TARGETNAME.secure $secure
-	}
-}
-
-$_TARGETNAME configure -event gdb-flash-erase-start {
-	set use_secure_workarea 0
-	# check if FLASH_OPTR.TZEN is enabled
-	set FLASH_OPTR [mrw 0x40022040]
-	if {[expr {$FLASH_OPTR & 0x80000000}] == 0} {
-		echo "TZEN option bit disabled"
-		ahb_ap_non_secure_access
-	} {
-		ahb_ap_secure_access
-		echo "TZEN option bit enabled"
-
-		# check if FLASH_OPTR.RDP is not Level 0.5
-		if {[expr {$FLASH_OPTR & 0xFF}] != 0x55} {
-			set use_secure_workarea 1
-		}
-	}
-
-	set workarea_addr [$_TARGETNAME cget -work-area-phys]
-	echo "workarea_addr $workarea_addr"
-
-	if {$use_secure_workarea} {
-		set workarea_addr [expr {$workarea_addr | 0x10000000}]
-	} {
-		set workarea_addr [expr {$workarea_addr & ~0x10000000}]
-	}
-
-	$_TARGETNAME configure -work-area-phys $workarea_addr
-}
-
-$_TARGETNAME configure -event trace-config {
-	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
-	# change this value accordingly to configure trace pins
-	# assignment
-	mmw 0xE0044004 0x00000020 0
-}
diff --git a/tcl/target/stm32u5x.cfg b/tcl/target/stm32u5x.cfg
index 2c2c0e0..b627d41 100644
--- a/tcl/target/stm32u5x.cfg
+++ b/tcl/target/stm32u5x.cfg
@@ -1,10 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 # script for stm32u5x family
+# stm32u5x devices support both JTAG and SWD transports.
 
-#
-# stm32u5 devices support both JTAG and SWD transports.
-#
 source [find target/swj-dp.tcl]
 source [find mem_helper.tcl]
 
@@ -14,78 +12,10 @@ if { [info exists CHIPNAME] } {
 	set _CHIPNAME stm32u5x
 }
 
-set _ENDIAN little
+source [find target/stm32x5x_common.cfg]
 
-# Work-area is a space in RAM used for flash programming
-# By default use 64kB
-if { [info exists WORKAREASIZE] } {
-	set _WORKAREASIZE $WORKAREASIZE
-} else {
-	set _WORKAREASIZE 0x10000
-}
-
-#jtag scan chain
-if { [info exists CPUTAPID] } {
-	set _CPUTAPID $CPUTAPID
-} else {
-	if { [using_jtag] } {
-		# See STM Document RM0438
-		# RM0456 Rev1, Section 65.2.8 JTAG debug port - Table 661. JTAG-DP data registers
-		# Corresponds to Cortex®-M33 JTAG debug port ID code
-		set _CPUTAPID 0x0ba04477
-	} {
-		# SWD IDCODE (single drop, arm)
-		set _CPUTAPID 0x0be12477
-	}
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
-
-if {[using_jtag]} {
-	jtag newtap $_CHIPNAME bs -irlen 5
-}
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
-
-# use non-secure RAM by default
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-# create sec/ns flash and otp memories (sizes will be probed)
-flash bank $_CHIPNAME.flash_ns      stm32l4x 0x08000000 0 0 0 $_TARGETNAME
-flash bank $_CHIPNAME.flash_alias_s stm32l4x 0x0C000000 0 0 0 $_TARGETNAME
-flash bank $_CHIPNAME.otp           stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME
-
-# Common knowledges tells JTAG speed should be <= F_CPU/6.
-# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
-# the safe side.
-#
-# Note that there is a pretty wide band where things are
-# more or less stable, see http://openocd.zylin.com/#/c/3366/
-adapter speed 500
-
-adapter srst delay 100
-if {[using_jtag]} {
-	jtag_ntrst_delay 100
-}
-
-reset_config srst_nogate
-
-if {![using_hla]} {
-	# if srst is not fitted use SYSRESETREQ to
-	# perform a soft reset
-	cortex_m reset_config sysresetreq
-}
-
-proc is_secure {} {
-	# read Debug Security Control and Status Regsiter (DSCSR) and check CDS (bit 16)
-	set DSCSR [mrw 0xE000EE08]
-	return [expr {($DSCSR & (1 << 16)) != 0}]
-}
-
-proc clock_config_160_mhz {} {
-	set offset [expr {[is_secure] ? 0x10000000 : 0}]
+proc stm32u5x_clock_config {} {
+	set offset [expr {[stm32x5x_is_secure] ? 0x10000000 : 0}]
 	# MCU clock is at MSI 4MHz after reset, set MCU freq at 160 MHz with PLL
 
 	# Enable voltage range 1 for frequency above 100 Mhz
@@ -117,91 +47,8 @@ proc clock_config_160_mhz {} {
 	while {([mrw [expr {0x46020C1C + $offset}]] & 0x0C) != 0x0C} {}
 }
 
-proc ahb_ap_non_secure_access {} {
-	# SPROT=1=Non Secure access, Priv=1
-	[[target current] cget -dap] apcsw 0x4B000000 0x4F000000
-}
-
-proc ahb_ap_secure_access {} {
-	# SPROT=0=Secure access, Priv=1
-	[[target current] cget -dap] apcsw 0x0B000000 0x4F000000
-}
-
 $_TARGETNAME configure -event reset-init {
-	clock_config_160_mhz
+	stm32u5x_clock_config
 	# Boost JTAG frequency
 	adapter speed 4000
 }
-
-$_TARGETNAME configure -event reset-start {
-	# Reset clock is MSI (4 MHz)
-	adapter speed 480
-}
-
-$_TARGETNAME configure -event examine-end {
-	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
-	mmw 0xE0044004 0x00000006 0
-
-	# Stop watchdog counters during halt
-	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
-	mmw 0xE0044008 0x00001800 0
-}
-
-$_TARGETNAME configure -event halted {
-	set secure [is_secure]
-
-	if {$secure} {
-		set secure_str "Secure"
-		ahb_ap_secure_access
-	} else {
-		set secure_str "Non-Secure"
-		ahb_ap_non_secure_access
-	}
-
-	# print the secure state only when it changes
-	set _TARGETNAME [target current]
-	global $_TARGETNAME.secure
-
-	if {![info exists $_TARGETNAME.secure] || $secure != [set $_TARGETNAME.secure]} {
-		echo "CPU in $secure_str state"
-		# update saved security state
-		set $_TARGETNAME.secure $secure
-	}
-}
-
-$_TARGETNAME configure -event gdb-flash-erase-start {
-	set use_secure_workarea 0
-	# check if FLASH_OPTR.TZEN is enabled
-	set FLASH_OPTR [mrw 0x40022040]
-	if {[expr {$FLASH_OPTR & 0x80000000}] == 0} {
-		echo "TZEN option bit disabled"
-		ahb_ap_non_secure_access
-	} else {
-		ahb_ap_secure_access
-		echo "TZEN option bit enabled"
-
-		# check if FLASH_OPTR.RDP is not Level 0.5
-		if {[expr {$FLASH_OPTR & 0xFF}] != 0x55} {
-			set use_secure_workarea 1
-		}
-	}
-
-	set _TARGETNAME [target current]
-	set workarea_addr [$_TARGETNAME cget -work-area-phys]
-	echo "workarea_addr $workarea_addr"
-
-	if {$use_secure_workarea} {
-		set workarea_addr [expr {$workarea_addr | 0x10000000}]
-	} else {
-		set workarea_addr [expr {$workarea_addr & ~0x10000000}]
-	}
-
-	$_TARGETNAME configure -work-area-phys $workarea_addr
-}
-
-$_TARGETNAME configure -event trace-config {
-	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
-	# change this value accordingly to configure trace pins
-	# assignment
-	mmw 0xE0044004 0x00000020 0
-}
diff --git a/tcl/target/stm32x5x_common.cfg b/tcl/target/stm32x5x_common.cfg
new file mode 100644
index 0000000..276d0cc
--- /dev/null
+++ b/tcl/target/stm32x5x_common.cfg
@@ -0,0 +1,154 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# common script for stm32l5x and stm32u5x families
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x10000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		# STM32L5x: RM0438 Rev5, Section 52.2.8 JTAG debug port - Table 425. JTAG-DP data registers
+		# STM32U5x: RM0456 Rev1, Section 65.2.8 JTAG debug port - Table 661. JTAG-DP data registers
+		# Corresponds to Cortex®-M33 JTAG debug port ID code
+		set _CPUTAPID 0x0ba04477
+	} {
+		# SWD IDCODE (single drop, arm)
+		set _CPUTAPID 0x0be12477
+	}
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+	jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+# use non-secure RAM by default
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# create sec/ns flash and otp memories (sizes will be probed)
+flash bank $_CHIPNAME.flash_ns      stm32l4x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.flash_alias_s stm32l4x 0x0C000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp           stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME
+
+# Common knowledge tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://review.openocd.org/3366
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+	jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+	# if srst is not fitted use SYSRESETREQ to
+	# perform a soft reset
+	cortex_m reset_config sysresetreq
+}
+
+proc stm32x5x_is_secure {} {
+	# read Debug Security Control and Status Register (DSCSR) and check CDS (bit 16)
+	set DSCSR [mrw 0xE000EE08]
+	return [expr {($DSCSR & (1 << 16)) != 0}]
+}
+
+proc stm32x5x_ahb_ap_non_secure_access {} {
+	# SPROT=1=Non Secure access, Priv=1
+	[[target current] cget -dap] apcsw 0x4B000000 0x4F000000
+}
+
+proc stm32x5x_ahb_ap_secure_access {} {
+	# SPROT=0=Secure access, Priv=1
+	[[target current] cget -dap] apcsw 0x0B000000 0x4F000000
+}
+
+$_TARGETNAME configure -event reset-start {
+	# Reset clock is MSI (4 MHz)
+	adapter speed 480
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+	mmw 0xE0044004 0x00000006 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0xE0044008 0x00001800 0
+}
+
+$_TARGETNAME configure -event halted {
+	set secure [stm32x5x_is_secure]
+
+	if {$secure} {
+		set secure_str "Secure"
+		stm32x5x_ahb_ap_secure_access
+	} else {
+		set secure_str "Non-Secure"
+		stm32x5x_ahb_ap_non_secure_access
+	}
+
+	# print the secure state only when it changes
+	set _TARGETNAME [target current]
+	global $_TARGETNAME.secure
+
+	if {![info exists $_TARGETNAME.secure] || $secure != [set $_TARGETNAME.secure]} {
+		echo "CPU in $secure_str state"
+		# update saved security state
+		set $_TARGETNAME.secure $secure
+	}
+}
+
+$_TARGETNAME configure -event gdb-flash-erase-start {
+	set use_secure_workarea 0
+	# check if FLASH_OPTR.TZEN is enabled
+	set FLASH_OPTR [mrw 0x40022040]
+	if {[expr {$FLASH_OPTR & 0x80000000}] == 0} {
+		echo "TZEN option bit disabled"
+		stm32x5x_ahb_ap_non_secure_access
+	} else {
+		stm32x5x_ahb_ap_secure_access
+		echo "TZEN option bit enabled"
+
+		# check if FLASH_OPTR.RDP is not Level 0.5
+		if {[expr {$FLASH_OPTR & 0xFF}] != 0x55} {
+			set use_secure_workarea 1
+		}
+	}
+
+	set _TARGETNAME [target current]
+	set workarea_addr [$_TARGETNAME cget -work-area-phys]
+	echo "workarea_addr $workarea_addr"
+
+	if {$use_secure_workarea} {
+		set workarea_addr [expr {$workarea_addr | 0x10000000}]
+	} else {
+		set workarea_addr [expr {$workarea_addr & ~0x10000000}]
+	}
+
+	$_TARGETNAME configure -work-area-phys $workarea_addr
+}
+
+$_TARGETNAME configure -event trace-config {
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0044004 0x00000020 0
+}