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| author | Tim Newsome <tim@sifive.com> | 2018-08-24 13:01:49 -0700 |
|---|---|---|
| committer | Tomas Vanek <vanekt@fbl.cz> | 2018-09-25 20:57:58 +0100 |
| commit | e2b6f347c72b1291c34cf23057d04edde6841670 (patch) | |
| tree | 23e22460322ef18dc0b264b6a963a21e917838e2 | |
| parent | b2d259f67cc3ee4b689e704228d97943bae94064 (diff) | |
| download | riscv-openocd-e2b6f347c72b1291c34cf23057d04edde6841670.zip riscv-openocd-e2b6f347c72b1291c34cf23057d04edde6841670.tar.gz riscv-openocd-e2b6f347c72b1291c34cf23057d04edde6841670.tar.bz2 | |
Clarify what exactly the RISC-V code supports.
Change-Id: I8da657426cc52c738ab41bfb0164cbc6721c0aef
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4655
Tested-by: jenkins
Reviewed-by: Philipp Guehring <pg@futureware.at>
Reviewed-by: Liviu Ionescu <ilg@livius.net>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
| -rw-r--r-- | doc/openocd.texi | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index e87d8c2..bbe6cff 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -9022,8 +9022,11 @@ Display all registers in @emph{group}. @section RISC-V Architecture @uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG -debug of targets that implement version 0.11 and 0.13 of the RISC-V Debug -Specification. +debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 32 +harts. (It's possible to increase this limit to 1024 by changing +RISCV_MAX_HARTS in riscv.h.) OpenOCD primarily supports 0.13 of the RISC-V +Debug Specification, but there is also support for legacy targets that +implement version 0.11. @subsection RISC-V Terminology |