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| author | Tomas Vanek <vanekt@fbl.cz> | 2019-01-19 10:26:38 +0100 |
|---|---|---|
| committer | Tomas Vanek <vanekt@fbl.cz> | 2019-02-04 10:25:44 +0000 |
| commit | 4b998cb5f5d2066e5e0197fcc460831b09813f70 (patch) | |
| tree | 6a998d8bd04eab85c44a1c66d3497755d3e259a7 | |
| parent | 5105e6037f16f3f1eda3d81d1749886b7e3049d8 (diff) | |
| download | riscv-openocd-4b998cb5f5d2066e5e0197fcc460831b09813f70.zip riscv-openocd-4b998cb5f5d2066e5e0197fcc460831b09813f70.tar.gz riscv-openocd-4b998cb5f5d2066e5e0197fcc460831b09813f70.tar.bz2 | |
cortex_m: fix stepping on FPB rev 1
Stepping in the maskisr auto mode sets breakpoint to step over interrupt
service tasks. If the device has FPB rev 1, setting hard breakpoint
is impossible on address over 0x1fffffff.
Use soft type breakpoint for adresses over 0x1fffffff if FPB is rev 1.
This may eventually fail if the code memory is not writeable, but there
is nothing to do in such case.
Change-Id: Ibdeeb506903a35d550b64f82c24c37a668de62b3
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4857
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
| -rw-r--r-- | src/target/cortex_m.c | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 3c97bc3..34a19e7 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -877,10 +877,17 @@ static int cortex_m_step(struct target *target, int current, else { /* Set a temporary break point */ - if (breakpoint) + if (breakpoint) { retval = cortex_m_set_breakpoint(target, breakpoint); - else - retval = breakpoint_add(target, pc_value, 2, BKPT_HARD); + } else { + enum breakpoint_type type = BKPT_HARD; + if (cortex_m->fp_rev == 0 && pc_value > 0x1FFFFFFF) { + /* FPB rev.1 cannot handle such addr, try BKPT instr */ + type = BKPT_SOFT; + } + retval = breakpoint_add(target, pc_value, 2, type); + } + bool tmp_bp_set = (retval == ERROR_OK); /* No more breakpoints left, just do a step */ |