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| author | Tim Newsome <tim@sifive.com> | 2020-08-24 15:42:29 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-08-24 15:42:29 -0700 |
| commit | ca6b1eff1dc8c5214b662259615b3cf5b024d121 (patch) | |
| tree | e55816663727679349dabb472f80747e0268584e | |
| parent | 920497c62f2ace333f49682e8dda0ba26c080387 (diff) | |
| download | riscv-openocd-ca6b1eff1dc8c5214b662259615b3cf5b024d121.zip riscv-openocd-ca6b1eff1dc8c5214b662259615b3cf5b024d121.tar.gz riscv-openocd-ca6b1eff1dc8c5214b662259615b3cf5b024d121.tar.bz2 | |
Update debug_defines.h from riscv-debug-spec (#515)
A ton of constants got a new prefix, so I made a lot of changes to
match, but no functional changes.
I did define DTM_DMI_MAX_ADDRESS_LENGTH in batch.c. That definition
never should have been in debug_defines.h, which I missed during code
review.
Change-Id: If5d86660f84bb0a3f2865fb36ef05d6630486d8b
| -rw-r--r-- | src/target/riscv/batch.c | 1 | ||||
| -rw-r--r-- | src/target/riscv/debug_defines.h | 2566 | ||||
| -rw-r--r-- | src/target/riscv/riscv-013.c | 916 |
3 files changed, 1783 insertions, 1700 deletions
diff --git a/src/target/riscv/batch.c b/src/target/riscv/batch.c index fb946b5..2f65193 100644 --- a/src/target/riscv/batch.c +++ b/src/target/riscv/batch.c @@ -9,6 +9,7 @@ #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1))) #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask))) +#define DTM_DMI_MAX_ADDRESS_LENGTH ((1<<DTM_DTMCS_ABITS_LENGTH)-1) #define DMI_SCAN_MAX_BIT_LENGTH (DTM_DMI_MAX_ADDRESS_LENGTH + DTM_DMI_DATA_LENGTH + DTM_DMI_OP_LENGTH) #define DMI_SCAN_BUF_SIZE (DIV_ROUND_UP(DMI_SCAN_MAX_BIT_LENGTH, 8)) diff --git a/src/target/riscv/debug_defines.h b/src/target/riscv/debug_defines.h index 7f3077c..cb518a8 100644 --- a/src/target/riscv/debug_defines.h +++ b/src/target/riscv/debug_defines.h @@ -1,22 +1,27 @@ +/* + * This file is auto-generated by running 'make debug_defines.h' in + * https://github.com/riscv/riscv-debug-spec/ (30b1a97) + */ + #define DTM_IDCODE 0x01 /* -* Identifies the release version of this part. + * Identifies the release version of this part. */ #define DTM_IDCODE_VERSION_OFFSET 28 #define DTM_IDCODE_VERSION_LENGTH 4 #define DTM_IDCODE_VERSION (0xfU << DTM_IDCODE_VERSION_OFFSET) /* -* Identifies the designer's part number of this part. + * Identifies the designer's part number of this part. */ #define DTM_IDCODE_PARTNUMBER_OFFSET 12 #define DTM_IDCODE_PARTNUMBER_LENGTH 16 #define DTM_IDCODE_PARTNUMBER (0xffffU << DTM_IDCODE_PARTNUMBER_OFFSET) /* -* Identifies the designer/manufacturer of this part. Bits 6:0 must be -* bits 6:0 of the designer/manufacturer's Identification Code as -* assigned by JEDEC Standard JEP106. Bits 10:7 contain the modulo-16 -* count of the number of continuation characters (0x7f) in that same -* Identification Code. + * Identifies the designer/manufacturer of this part. Bits 6:0 must be + * bits 6:0 of the designer/manufacturer's Identification Code as + * assigned by JEDEC Standard JEP106. Bits 10:7 contain the modulo-16 + * count of the number of continuation characters (0x7f) in that same + * Identification Code. */ #define DTM_IDCODE_MANUFID_OFFSET 1 #define DTM_IDCODE_MANUFID_LENGTH 11 @@ -26,275 +31,276 @@ #define DTM_IDCODE_1 (0x1U << DTM_IDCODE_1_OFFSET) #define DTM_DTMCS 0x10 /* -* Writing 1 to this bit does a hard reset of the DTM, -* causing the DTM to forget about any outstanding DMI transactions. -* In general this should only be used when the Debugger has -* reason to expect that the outstanding DMI transaction will never -* complete (e.g. a reset condition caused an inflight DMI transaction to -* be cancelled). + * Writing 1 to this bit does a hard reset of the DTM, + * causing the DTM to forget about any outstanding DMI transactions, and + * returning all registers and internal state to their reset value. + * In general this should only be used when the Debugger has + * reason to expect that the outstanding DMI transaction will never + * complete (e.g. a reset condition caused an inflight DMI transaction to + * be cancelled). */ #define DTM_DTMCS_DMIHARDRESET_OFFSET 17 #define DTM_DTMCS_DMIHARDRESET_LENGTH 1 #define DTM_DTMCS_DMIHARDRESET (0x1U << DTM_DTMCS_DMIHARDRESET_OFFSET) /* -* Writing 1 to this bit clears the sticky error state -* and allows the DTM to retry or complete the previous -* transaction. + * Writing 1 to this bit clears the sticky error state, but does + * not affect outstanding DMI transactions. */ #define DTM_DTMCS_DMIRESET_OFFSET 16 #define DTM_DTMCS_DMIRESET_LENGTH 1 #define DTM_DTMCS_DMIRESET (0x1U << DTM_DTMCS_DMIRESET_OFFSET) /* -* This is a hint to the debugger of the minimum number of -* cycles a debugger should spend in -* Run-Test/Idle after every DMI scan to avoid a `busy' -* return code (\Fdmistat of 3). A debugger must still -* check \Fdmistat when necessary. -* -* 0: It is not necessary to enter Run-Test/Idle at all. -* -* 1: Enter Run-Test/Idle and leave it immediately. -* -* 2: Enter Run-Test/Idle and stay there for 1 cycle before leaving. -* -* And so on. + * This is a hint to the debugger of the minimum number of + * cycles a debugger should spend in + * Run-Test/Idle after every DMI scan to avoid a `busy' + * return code (\FdtmDtmcsDmistat of 3). A debugger must still + * check \FdtmDtmcsDmistat when necessary. + * + * 0: It is not necessary to enter Run-Test/Idle at all. + * + * 1: Enter Run-Test/Idle and leave it immediately. + * + * 2: Enter Run-Test/Idle and stay there for 1 cycle before leaving. + * + * And so on. */ #define DTM_DTMCS_IDLE_OFFSET 12 #define DTM_DTMCS_IDLE_LENGTH 3 #define DTM_DTMCS_IDLE (0x7U << DTM_DTMCS_IDLE_OFFSET) /* -* 0: No error. -* -* 1: Reserved. Interpret the same as 2. -* -* 2: An operation failed (resulted in \Fop of 2). -* -* 3: An operation was attempted while a DMI access was still in -* progress (resulted in \Fop of 3). + * 0: No error. + * + * 1: Reserved. Interpret the same as 2. + * + * 2: An operation failed (resulted in \FdtmDmiOp of 2). + * + * 3: An operation was attempted while a DMI access was still in + * progress (resulted in \FdtmDmiOp of 3). */ #define DTM_DTMCS_DMISTAT_OFFSET 10 #define DTM_DTMCS_DMISTAT_LENGTH 2 #define DTM_DTMCS_DMISTAT (0x3U << DTM_DTMCS_DMISTAT_OFFSET) /* -* The size of \Faddress in \Rdmi. + * The size of \FdmSbaddressZeroAddress in \RdtmDmi. */ #define DTM_DTMCS_ABITS_OFFSET 4 #define DTM_DTMCS_ABITS_LENGTH 6 #define DTM_DTMCS_ABITS (0x3fU << DTM_DTMCS_ABITS_OFFSET) /* -* 0: Version described in spec version 0.11. -* -* 1: Version described in spec version 0.13. -* -* 15: Version not described in any available version of this spec. + * 0: Version described in spec version 0.11. + * + * 1: Version described in spec version 0.13. + * + * 15: Version not described in any available version of this spec. */ #define DTM_DTMCS_VERSION_OFFSET 0 #define DTM_DTMCS_VERSION_LENGTH 4 #define DTM_DTMCS_VERSION (0xfU << DTM_DTMCS_VERSION_OFFSET) #define DTM_DMI 0x11 /* -* Address used for DMI access. In Update-DR this value is used -* to access the DM over the DMI. + * Address used for DMI access. In Update-DR this value is used + * to access the DM over the DMI. */ #define DTM_DMI_ADDRESS_OFFSET 34 #define DTM_DMI_ADDRESS_LENGTH abits -#define DTM_DMI_MAX_ADDRESS_LENGTH 63 -#define DTM_DMI_ADDRESS (((1L<<abits)-1) << DTM_DMI_ADDRESS_OFFSET) +#define DTM_DMI_ADDRESS (((1L << abits) - 1) << DTM_DMI_ADDRESS_OFFSET) /* -* The data to send to the DM over the DMI during Update-DR, and -* the data returned from the DM as a result of the previous operation. + * The data to send to the DM over the DMI during Update-DR, and + * the data returned from the DM as a result of the previous operation. */ #define DTM_DMI_DATA_OFFSET 2 #define DTM_DMI_DATA_LENGTH 32 #define DTM_DMI_DATA (0xffffffffULL << DTM_DMI_DATA_OFFSET) /* -* When the debugger writes this field, it has the following meaning: -* -* 0: Ignore \Fdata and \Faddress. (nop) -* -* Don't send anything over the DMI during Update-DR. -* This operation should never result in a busy or error response. -* The address and data reported in the following Capture-DR -* are undefined. -* -* 1: Read from \Faddress. (read) -* -* 2: Write \Fdata to \Faddress. (write) -* -* 3: Reserved. -* -* When the debugger reads this field, it means the following: -* -* 0: The previous operation completed successfully. -* -* 1: Reserved. -* -* 2: A previous operation failed. The data scanned into \Rdmi in -* this access will be ignored. This status is sticky and can be -* cleared by writing \Fdmireset in \Rdtmcs. -* -* This indicates that the DM itself responded with an error. -* There are no specified cases in which the DM would -* respond with an error, and DMI is not required to support -* returning errors. -* -* 3: An operation was attempted while a DMI request is still in -* progress. The data scanned into \Rdmi in this access will be -* ignored. This status is sticky and can be cleared by writing -* \Fdmireset in \Rdtmcs. If a debugger sees this status, it -* needs to give the target more TCK edges between Update-DR and -* Capture-DR. The simplest way to do that is to add extra transitions -* in Run-Test/Idle. + * When the debugger writes this field, it has the following meaning: + * + * 0: Ignore \FdmSbdataZeroData and \FdmSbaddressZeroAddress. (nop) + * + * Don't send anything over the DMI during Update-DR. + * This operation should never result in a busy or error response. + * The address and data reported in the following Capture-DR + * are undefined. + * + * 1: Read from \FdmSbaddressZeroAddress. (read) + * + * 2: Write \FdmSbdataZeroData to \FdmSbaddressZeroAddress. (write) + * + * 3: Reserved. + * + * When the debugger reads this field, it means the following: + * + * 0: The previous operation completed successfully. + * + * 1: Reserved. + * + * 2: A previous operation failed. The data scanned into \RdtmDmi in + * this access will be ignored. This status is sticky and can be + * cleared by writing \FdtmDtmcsDmireset in \RdtmDtmcs. + * + * This indicates that the DM itself responded with an error. + * There are no specified cases in which the DM would + * respond with an error, and DMI is not required to support + * returning errors. + * + * 3: An operation was attempted while a DMI request is still in + * progress. The data scanned into \RdtmDmi in this access will be + * ignored. This status is sticky and can be cleared by writing + * \FdtmDtmcsDmireset in \RdtmDtmcs. If a debugger sees this status, it + * needs to give the target more TCK edges between Update-DR and + * Capture-DR. The simplest way to do that is to add extra transitions + * in Run-Test/Idle. */ #define DTM_DMI_OP_OFFSET 0 #define DTM_DMI_OP_LENGTH 2 #define DTM_DMI_OP (0x3ULL << DTM_DMI_OP_OFFSET) #define CSR_DCSR 0x7b0 /* -* 0: There is no external debug support. -* -* 4: External debug support exists as it is described in this document. -* -* 15: There is external debug support, but it does not conform to any -* available version of this spec. + * 0: There is no external debug support. + * + * 4: External debug support exists as it is described in this document. + * + * 15: There is external debug support, but it does not conform to any + * available version of this spec. */ #define CSR_DCSR_XDEBUGVER_OFFSET 28 #define CSR_DCSR_XDEBUGVER_LENGTH 4 #define CSR_DCSR_XDEBUGVER (0xfU << CSR_DCSR_XDEBUGVER_OFFSET) /* -* 0: {\tt ebreak} instructions in M-mode behave as described in the -* Privileged Spec. -* -* 1: {\tt ebreak} instructions in M-mode enter Debug Mode. + * 0: {\tt ebreak} instructions in M-mode behave as described in the + * Privileged Spec. + * + * 1: {\tt ebreak} instructions in M-mode enter Debug Mode. */ #define CSR_DCSR_EBREAKM_OFFSET 15 #define CSR_DCSR_EBREAKM_LENGTH 1 #define CSR_DCSR_EBREAKM (0x1U << CSR_DCSR_EBREAKM_OFFSET) /* -* 0: {\tt ebreak} instructions in S-mode behave as described in the -* Privileged Spec. -* -* 1: {\tt ebreak} instructions in S-mode enter Debug Mode. + * 0: {\tt ebreak} instructions in S-mode behave as described in the + * Privileged Spec. + * + * 1: {\tt ebreak} instructions in S-mode enter Debug Mode. + * + * This bit is hardwired to 0 if the hart does not support S mode. */ #define CSR_DCSR_EBREAKS_OFFSET 13 #define CSR_DCSR_EBREAKS_LENGTH 1 #define CSR_DCSR_EBREAKS (0x1U << CSR_DCSR_EBREAKS_OFFSET) /* -* 0: {\tt ebreak} instructions in U-mode behave as described in the -* Privileged Spec. -* -* 1: {\tt ebreak} instructions in U-mode enter Debug Mode. + * 0: {\tt ebreak} instructions in U-mode behave as described in the + * Privileged Spec. + * + * 1: {\tt ebreak} instructions in U-mode enter Debug Mode. + * + * This bit is hardwired to 0 if the hart does not support U mode. */ #define CSR_DCSR_EBREAKU_OFFSET 12 #define CSR_DCSR_EBREAKU_LENGTH 1 #define CSR_DCSR_EBREAKU (0x1U << CSR_DCSR_EBREAKU_OFFSET) /* -* 0: Interrupts are disabled during single stepping. -* -* 1: Interrupts are enabled during single stepping. -* -* Implementations may hard wire this bit to 0. -* In that case interrupt behavior can be emulated by the debugger. -* -* The debugger must not change the value of this bit while the hart -* is running. + * 0: Interrupts (including NMI) are disabled during single stepping. + * + * 1: Interrupts (including NMI) are enabled during single stepping. + * + * Implementations may hard wire this bit to 0. + * In that case interrupt behavior can be emulated by the debugger. + * + * The debugger must not change the value of this bit while the hart + * is running. */ #define CSR_DCSR_STEPIE_OFFSET 11 #define CSR_DCSR_STEPIE_LENGTH 1 #define CSR_DCSR_STEPIE (0x1U << CSR_DCSR_STEPIE_OFFSET) /* -* 0: Increment counters as usual. -* -* 1: Don't increment any hart-local counters while in Debug Mode or -* on {\tt ebreak} instructions that cause entry into Debug Mode. -* These counters include the {\tt instret} CSR. On single-hart cores -* {\tt cycle} should be stopped, but on multi-hart cores it must keep -* incrementing. -* -* An implementation may hardwire this bit to 0 or 1. + * 0: Increment counters as usual. + * + * 1: Don't increment any hart-local counters while in Debug Mode or + * on {\tt ebreak} instructions that cause entry into Debug Mode. + * These counters include the {\tt instret} CSR. On single-hart cores + * {\tt cycle} should be stopped, but on multi-hart cores it must keep + * incrementing. + * + * An implementation may hardwire this bit to 0 or 1. */ #define CSR_DCSR_STOPCOUNT_OFFSET 10 #define CSR_DCSR_STOPCOUNT_LENGTH 1 #define CSR_DCSR_STOPCOUNT (0x1U << CSR_DCSR_STOPCOUNT_OFFSET) /* -* 0: Increment timers as usual. -* -* 1: Don't increment any hart-local timers while in Debug Mode. -* -* An implementation may hardwire this bit to 0 or 1. + * 0: Increment timers as usual. + * + * 1: Don't increment any hart-local timers while in Debug Mode. + * + * An implementation may hardwire this bit to 0 or 1. */ #define CSR_DCSR_STOPTIME_OFFSET 9 #define CSR_DCSR_STOPTIME_LENGTH 1 #define CSR_DCSR_STOPTIME (0x1U << CSR_DCSR_STOPTIME_OFFSET) /* -* Explains why Debug Mode was entered. -* -* When there are multiple reasons to enter Debug Mode in a single -* cycle, hardware should set \Fcause to the cause with the highest -* priority. -* -* 1: An {\tt ebreak} instruction was executed. (priority 3) -* -* 2: The Trigger Module caused a breakpoint exception. (priority 4) -* -* 3: The debugger requested entry to Debug Mode using \Fhaltreq. -* (priority 1) -* -* 4: The hart single stepped because \Fstep was set. (priority 0, lowest) -* -* 5: The hart halted directly out of reset due to \Fresethaltreq. It -* is also acceptable to report 3 when this happens. (priority 2) -* -* 6: The hart halted because it's part of a halt group. (priority 5, -* highest) Harts may report 3 for this cause instead. -* -* Other values are reserved for future use. + * Explains why Debug Mode was entered. + * + * When there are multiple reasons to enter Debug Mode in a single + * cycle, hardware should set \FcsrDcsrCause to the cause with the highest + * priority. + * + * 1: An {\tt ebreak} instruction was executed. (priority 3) + * + * 2: The Trigger Module caused a breakpoint exception. (priority 4) + * + * 3: The debugger requested entry to Debug Mode using \FdmDmcontrolHaltreq. + * (priority 1) + * + * 4: The hart single stepped because \FcsrDcsrStep was set. (priority 0, lowest) + * + * 5: The hart halted directly out of reset due to \Fresethaltreq. It + * is also acceptable to report 3 when this happens. (priority 2) + * + * 6: The hart halted because it's part of a halt group. (priority 5, + * highest) Harts may report 3 for this cause instead. + * + * Other values are reserved for future use. */ #define CSR_DCSR_CAUSE_OFFSET 6 #define CSR_DCSR_CAUSE_LENGTH 3 #define CSR_DCSR_CAUSE (0x7U << CSR_DCSR_CAUSE_OFFSET) /* -* 0: \Fmprv in \Rmstatus is ignored in Debug Mode. -* -* 1: \Fmprv in \Rmstatus takes effect in Debug Mode. -* -* Implementing this bit is optional. It may be tied to either 0 or 1. + * 0: \FcsrMcontrolMprv in \Rmstatus is ignored in Debug Mode. + * + * 1: \FcsrMcontrolMprv in \Rmstatus takes effect in Debug Mode. + * + * Implementing this bit is optional. It may be tied to either 0 or 1. */ #define CSR_DCSR_MPRVEN_OFFSET 4 #define CSR_DCSR_MPRVEN_LENGTH 1 #define CSR_DCSR_MPRVEN (0x1U << CSR_DCSR_MPRVEN_OFFSET) /* -* When set, there is a Non-Maskable-Interrupt (NMI) pending for the hart. -* -* Since an NMI can indicate a hardware error condition, -* reliable debugging may no longer be possible once this bit becomes set. -* This is implementation-dependent. + * When set, there is a Non-Maskable-Interrupt (NMI) pending for the hart. + * + * Since an NMI can indicate a hardware error condition, + * reliable debugging may no longer be possible once this bit becomes set. + * This is implementation-dependent. */ #define CSR_DCSR_NMIP_OFFSET 3 #define CSR_DCSR_NMIP_LENGTH 1 #define CSR_DCSR_NMIP (0x1U << CSR_DCSR_NMIP_OFFSET) /* -* When set and not in Debug Mode, the hart will only execute a single -* instruction and then enter Debug Mode. -* If the instruction does not complete due to an exception, -* the hart will immediately enter Debug Mode before executing -* the trap handler, with appropriate exception registers set. -* -* The debugger must not change the value of this bit while the hart -* is running. + * When set and not in Debug Mode, the hart will only execute a single + * instruction and then enter Debug Mode. See Section~\ref{stepBit} + * for details. + * + * The debugger must not change the value of this bit while the hart + * is running. */ #define CSR_DCSR_STEP_OFFSET 2 #define CSR_DCSR_STEP_LENGTH 1 #define CSR_DCSR_STEP (0x1U << CSR_DCSR_STEP_OFFSET) /* -* Contains the privilege level the hart was operating in when Debug -* Mode was entered. The encoding is described in Table -* \ref{tab:privlevel}. A debugger can change this value to change -* the hart's privilege level when exiting Debug Mode. -* -* Not all privilege levels are supported on all harts. If the -* encoding written is not supported or the debugger is not allowed to -* change to it, the hart may change to any supported privilege level. + * Contains the privilege level the hart was operating in when Debug + * Mode was entered. The encoding is described in Table + * \ref{tab:privlevel}. A debugger can change this value to change + * the hart's privilege level when exiting Debug Mode. + * + * Not all privilege levels are supported on all harts. If the + * encoding written is not supported or the debugger is not allowed to + * change to it, the hart may change to any supported privilege level. */ #define CSR_DCSR_PRV_OFFSET 0 #define CSR_DCSR_PRV_LENGTH 2 @@ -302,134 +308,135 @@ #define CSR_DPC 0x7b1 #define CSR_DPC_DPC_OFFSET 0 #define CSR_DPC_DPC_LENGTH DXLEN -#define CSR_DPC_DPC (((1L<<DXLEN)-1) << CSR_DPC_DPC_OFFSET) +#define CSR_DPC_DPC (((1L << DXLEN) - 1) << CSR_DPC_DPC_OFFSET) #define CSR_DSCRATCH0 0x7b2 #define CSR_DSCRATCH1 0x7b3 #define CSR_TSELECT 0x7a0 #define CSR_TSELECT_INDEX_OFFSET 0 #define CSR_TSELECT_INDEX_LENGTH XLEN -#define CSR_TSELECT_INDEX (((1L<<XLEN)-1) << CSR_TSELECT_INDEX_OFFSET) +#define CSR_TSELECT_INDEX (((1L << XLEN) - 1) << CSR_TSELECT_INDEX_OFFSET) #define CSR_TDATA1 0x7a1 /* -* 0: There is no trigger at this \Rtselect. -* -* 1: The trigger is a legacy SiFive address match trigger. These -* should not be implemented and aren't further documented here. -* -* 2: The trigger is an address/data match trigger. The remaining bits -* in this register act as described in \Rmcontrol. -* -* 3: The trigger is an instruction count trigger. The remaining bits -* in this register act as described in \Ricount. -* -* 4: The trigger is an interrupt trigger. The remaining bits -* in this register act as described in \Ritrigger. -* -* 5: The trigger is an exception trigger. The remaining bits -* in this register act as described in \Retrigger. -* -* 12--14: These trigger types are available for non-standard use. -* -* 15: This trigger exists (so enumeration shouldn't terminate), but -* is not currently available. -* -* Other values are reserved for future use. + * 0: There is no trigger at this \RcsrTselect. + * + * 1: The trigger is a legacy SiFive address match trigger. These + * should not be implemented and aren't further documented here. + * + * 2: The trigger is an address/data match trigger. The remaining bits + * in this register act as described in \RcsrMcontrol. + * + * 3: The trigger is an instruction count trigger. The remaining bits + * in this register act as described in \RcsrIcount. + * + * 4: The trigger is an interrupt trigger. The remaining bits + * in this register act as described in \RcsrItrigger. + * + * 5: The trigger is an exception trigger. The remaining bits + * in this register act as described in \RcsrEtrigger. + * + * 12--14: These trigger types are available for non-standard use. + * + * 15: This trigger exists (so enumeration shouldn't terminate), but + * is not currently available. + * + * Other values are reserved for future use. */ #define CSR_TDATA1_TYPE_OFFSET (XLEN-4) #define CSR_TDATA1_TYPE_LENGTH 4 #define CSR_TDATA1_TYPE (0xfULL << CSR_TDATA1_TYPE_OFFSET) /* -* 0: Both Debug and M-mode can write the {\tt tdata} registers at the -* selected \Rtselect. -* -* 1: Only Debug Mode can write the {\tt tdata} registers at the -* selected \Rtselect. Writes from other modes are ignored. -* -* This bit is only writable from Debug Mode. + * If \FcsrTdataOneType is 0, then this bit is hard-wired to 0. + * + * 0: Both Debug and M-mode can write the {\tt tdata} registers at the + * selected \RcsrTselect. + * + * 1: Only Debug Mode can write the {\tt tdata} registers at the + * selected \RcsrTselect. Writes from other modes are ignored. + * + * This bit is only writable from Debug Mode. + * When clearing this bit, the debugger should also clear the action field + * (whose location depends on \FcsrTdataOneType). */ #define CSR_TDATA1_DMODE_OFFSET (XLEN-5) #define CSR_TDATA1_DMODE_LENGTH 1 #define CSR_TDATA1_DMODE (0x1ULL << CSR_TDATA1_DMODE_OFFSET) /* -* Trigger-specific data. + * If \FcsrTdataOneType is 0, then this field is hard-wired to 0. + * + * Trigger-specific data. */ #define CSR_TDATA1_DATA_OFFSET 0 #define CSR_TDATA1_DATA_LENGTH (XLEN - 5) -#define CSR_TDATA1_DATA (((1L<<XLEN - 5)-1) << CSR_TDATA1_DATA_OFFSET) +#define CSR_TDATA1_DATA (((1L << XLEN - 5) - 1) << CSR_TDATA1_DATA_OFFSET) #define CSR_TDATA2 0x7a2 #define CSR_TDATA2_DATA_OFFSET 0 #define CSR_TDATA2_DATA_LENGTH XLEN -#define CSR_TDATA2_DATA (((1L<<XLEN)-1) << CSR_TDATA2_DATA_OFFSET) +#define CSR_TDATA2_DATA (((1L << XLEN) - 1) << CSR_TDATA2_DATA_OFFSET) #define CSR_TDATA3 0x7a3 #define CSR_TDATA3_DATA_OFFSET 0 #define CSR_TDATA3_DATA_LENGTH XLEN -#define CSR_TDATA3_DATA (((1L<<XLEN)-1) << CSR_TDATA3_DATA_OFFSET) +#define CSR_TDATA3_DATA (((1L << XLEN) - 1) << CSR_TDATA3_DATA_OFFSET) #define CSR_TINFO 0x7a4 /* -* One bit for each possible \Ftype enumerated in \Rtdataone. Bit N -* corresponds to type N. If the bit is set, then that type is -* supported by the currently selected trigger. -* -* If the currently selected trigger doesn't exist, this field -* contains 1. -* -* If \Ftype is not writable, this register may be unimplemented, in -* which case reading it causes an illegal instruction exception. In -* this case the debugger can read the only supported type from -* \Rtdataone. + * One bit for each possible \FcsrTdataOneType enumerated in \RcsrTdataOne. Bit N + * corresponds to type N. If the bit is set, then that type is + * supported by the currently selected trigger. + * + * If the currently selected trigger doesn't exist, this field + * contains 1. */ #define CSR_TINFO_INFO_OFFSET 0 #define CSR_TINFO_INFO_LENGTH 16 #define CSR_TINFO_INFO (0xffffULL << CSR_TINFO_INFO_OFFSET) #define CSR_TCONTROL 0x7a5 /* -* M-mode previous trigger enable field. -* -* When a trap into M-mode is taken, \Fmpte is set to the value of -* \Fmte. + * M-mode previous trigger enable field. + * + * When a trap into M-mode is taken, \FcsrTcontrolMpte is set to the value of + * \FcsrTcontrolMte. */ #define CSR_TCONTROL_MPTE_OFFSET 7 #define CSR_TCONTROL_MPTE_LENGTH 1 #define CSR_TCONTROL_MPTE (0x1ULL << CSR_TCONTROL_MPTE_OFFSET) /* -* M-mode trigger enable field. -* -* 0: Triggers with action=0 do not match/fire while the hart is in M-mode. -* -* 1: Triggers do match/fire while the hart is in M-mode. -* -* When a trap into M-mode is taken, \Fmte is set to 0. When {\tt -* mret} is executed, \Fmte is set to the value of \Fmpte. + * M-mode trigger enable field. + * + * 0: Triggers with action=0 do not match/fire while the hart is in M-mode. + * + * 1: Triggers do match/fire while the hart is in M-mode. + * + * When a trap into M-mode is taken, \FcsrTcontrolMte is set to 0. When {\tt + * mret} is executed, \FcsrTcontrolMte is set to the value of \FcsrTcontrolMpte. */ #define CSR_TCONTROL_MTE_OFFSET 3 #define CSR_TCONTROL_MTE_LENGTH 1 #define CSR_TCONTROL_MTE (0x1ULL << CSR_TCONTROL_MTE_OFFSET) #define CSR_MCONTEXT 0x7a8 /* -* Machine mode software can write a context number to this register, -* which can be used to set triggers that only fire in that specific -* context. -* -* An implementation may tie any number of upper bits in this field to -* 0. It's recommended to implement no more than 6 bits on RV32, and -* 13 on RV64. + * Machine mode software can write a context number to this register, + * which can be used to set triggers that only fire in that specific + * context. + * + * An implementation may tie any number of upper bits in this field to + * 0. It's recommended to implement no more than 6 bits on RV32, and + * 13 on RV64. */ #define CSR_MCONTEXT_MCONTEXT_OFFSET 0 #define CSR_MCONTEXT_MCONTEXT_LENGTH XLEN -#define CSR_MCONTEXT_MCONTEXT (((1L<<XLEN)-1) << CSR_MCONTEXT_MCONTEXT_OFFSET) +#define CSR_MCONTEXT_MCONTEXT (((1L << XLEN) - 1) << CSR_MCONTEXT_MCONTEXT_OFFSET) #define CSR_SCONTEXT 0x7aa /* -* Supervisor mode software can write a context number to this -* register, which can be used to set triggers that only fire in that -* specific context. -* -* An implementation may tie any number of high bits in this field to -* 0. It's recommended to implement no more than 16 bits on RV32, and -* 34 on RV64. + * Supervisor mode software can write a context number to this + * register, which can be used to set triggers that only fire in that + * specific context. + * + * An implementation may tie any number of high bits in this field to + * 0. It's recommended to implement no more than 16 bits on RV32, and + * 34 on RV64. */ #define CSR_SCONTEXT_DATA_OFFSET 0 #define CSR_SCONTEXT_DATA_LENGTH XLEN -#define CSR_SCONTEXT_DATA (((1L<<XLEN)-1) << CSR_SCONTEXT_DATA_OFFSET) +#define CSR_SCONTEXT_DATA (((1L << XLEN) - 1) << CSR_SCONTEXT_DATA_OFFSET) #define CSR_MCONTROL 0x7a1 #define CSR_MCONTROL_TYPE_OFFSET (XLEN-4) #define CSR_MCONTROL_TYPE_LENGTH 4 @@ -438,208 +445,233 @@ #define CSR_MCONTROL_DMODE_LENGTH 1 #define CSR_MCONTROL_DMODE (0x1ULL << CSR_MCONTROL_DMODE_OFFSET) /* -* Specifies the largest naturally aligned powers-of-two (NAPOT) range -* supported by the hardware when \Fmatch is 1. The value is the -* logarithm base 2 of the -* number of bytes in that range. A value of 0 indicates that only -* exact value matches are supported (one byte range). A value of 63 -* corresponds to the maximum NAPOT range, which is $2^{63}$ bytes in -* size. + * Specifies the largest naturally aligned powers-of-two (NAPOT) range + * supported by the hardware when \FcsrMcontrolMatch is 1. The value is the + * logarithm base 2 of the + * number of bytes in that range. A value of 0 indicates that only + * exact value matches are supported (one byte range). A value of 63 + * corresponds to the maximum NAPOT range, which is $2^{63}$ bytes in + * size. */ #define CSR_MCONTROL_MASKMAX_OFFSET (XLEN-11) #define CSR_MCONTROL_MASKMAX_LENGTH 6 #define CSR_MCONTROL_MASKMAX (0x3fULL << CSR_MCONTROL_MASKMAX_OFFSET) /* -* This field only exists if XLEN is greater than 32. In that case it -* extends \Fsize. If it does not exist then hardware operates as if -* the field contains 0. + * This field only exists when XLEN is at least 64. + * It contains the 2 high bits of the access size. The low bits + * come from \FcsrMcontrolSizelo. See \FcsrMcontrolSizelo for how this + * is used. */ #define CSR_MCONTROL_SIZEHI_OFFSET 21 #define CSR_MCONTROL_SIZEHI_LENGTH 2 #define CSR_MCONTROL_SIZEHI (0x3ULL << CSR_MCONTROL_SIZEHI_OFFSET) /* -* If this optional bit is implemented, the hardware sets it when this -* trigger matches. The trigger's user can set or clear it at any -* time. It is used to determine which -* trigger(s) matched. If the bit is not implemented, it is always 0 -* and writing it has no effect. + * If this bit is implemented, the hardware sets it when this + * trigger matches. The trigger's user can set or clear it at any + * time. It is used to determine which + * trigger(s) matched. If the bit is not implemented, it is always 0 + * and writing it has no effect. */ #define CSR_MCONTROL_HIT_OFFSET 20 #define CSR_MCONTROL_HIT_LENGTH 1 #define CSR_MCONTROL_HIT (0x1ULL << CSR_MCONTROL_HIT_OFFSET) /* -* 0: Perform a match on the virtual base address of the access. -* (E.g. on a 32-bit read from 0x4000, the base address is 0x4000.) -* -* 1: Perform a match on the data value loaded or stored, or the -* instruction executed. + * 0: Perform a match on the lowest virtual address of the access. In + * addition, it is recommended that the trigger also fires if any of + * the other accessed virtual addresses match. + * (E.g. on a 32-bit read from 0x4000, the lowest address is 0x4000 + * and the other addresses are 0x4001, 0x4002, and 0x4003.) + * + * 1: Perform a match on the data value loaded or stored, or the + * instruction executed. */ #define CSR_MCONTROL_SELECT_OFFSET 19 #define CSR_MCONTROL_SELECT_LENGTH 1 #define CSR_MCONTROL_SELECT (0x1ULL << CSR_MCONTROL_SELECT_OFFSET) /* -* 0: The action for this trigger will be taken just before the -* instruction that triggered it is executed, but after all preceding -* instructions are committed. -* -* 1: The action for this trigger will be taken after the instruction -* that triggered it is executed. It should be taken before the next -* instruction is executed, but it is better to implement triggers and -* not implement that suggestion than to not implement them at all. -* -* Most hardware will only implement one timing or the other, possibly -* dependent on \Fselect, \Fexecute, \Fload, and \Fstore. This bit -* primarily exists for the hardware to communicate to the debugger -* what will happen. Hardware may implement the bit fully writable, in -* which case the debugger has a little more control. -* -* Data load triggers with \Ftiming of 0 will result in the same load -* happening again when the debugger lets the hart run. For data load -* triggers, debuggers must first attempt to set the breakpoint with -* \Ftiming of 1. -* -* A chain of triggers that don't all have the same \Ftiming value -* will never fire (unless consecutive instructions match the -* appropriate triggers). -* -* If a trigger with \Ftiming of 0 matches, it is -* implementation-dependent whether that prevents a trigger with -* \Ftiming of 1 matching as well. + * 0: The action for this trigger will be taken just before the + * instruction that triggered it is executed, but after all preceding + * instructions are committed. \Rmepc or \RcsrDpc (depending on + * \FcsrMcontrolAction) must be set to the virtual address of the + * instruction that matched. + * + * If this is combined with \FcsrMcontrolLoad then a memory access will be + * performed (including any side effects of performing such an access) even + * though the load will not update its destination register. Debuggers + * should consider this when setting such breakpoints on, for example, + * memory-mapped I/O addresses. + * + * 1: The action for this trigger will be taken after the instruction + * that triggered it is executed. It should be taken before the next + * instruction is executed, but it is better to implement triggers imprecisely + * than to not implement them at all. + * \Rmepc or \RcsrDpc (depending on \FcsrMcontrolAction) must be set to + * the virtual address of the next instruction that must be executed to + * preserve the program flow. + * + * Most hardware will only implement one timing or the other, possibly + * dependent on \FcsrMcontrolSelect, \FcsrMcontrolExecute, + * \FcsrMcontrolLoad, and \FcsrMcontrolStore. This bit + * primarily exists for the hardware to communicate to the debugger + * what will happen. Hardware may implement the bit fully writable, in + * which case the debugger has a little more control. + * + * Data load triggers with \FcsrMcontrolTiming of 0 will result in the same load + * happening again when the debugger lets the hart run. For data load + * triggers, debuggers must first attempt to set the breakpoint with + * \FcsrMcontrolTiming of 1. + * + * If a trigger with \FcsrMcontrolTiming of 0 matches, it is + * implementation-dependent whether that prevents a trigger with + * \FcsrMcontrolTiming of 1 matching as well. */ #define CSR_MCONTROL_TIMING_OFFSET 18 #define CSR_MCONTROL_TIMING_LENGTH 1 #define CSR_MCONTROL_TIMING (0x1ULL << CSR_MCONTROL_TIMING_OFFSET) /* -* This field contains the 2 low bits of \Fsize. The high bits come -* from \Fsizehi. The combined value is interpreted as follows: -* -* 0: The trigger will attempt to match against an access of any size. -* The behavior is only well-defined if $|select|=0$, or if the access -* size is XLEN. -* -* 1: The trigger will only match against 8-bit memory accesses. -* -* 2: The trigger will only match against 16-bit memory accesses or -* execution of 16-bit instructions. -* -* 3: The trigger will only match against 32-bit memory accesses or -* execution of 32-bit instructions. -* -* 4: The trigger will only match against execution of 48-bit instructions. -* -* 5: The trigger will only match against 64-bit memory accesses or -* execution of 64-bit instructions. -* -* 6: The trigger will only match against execution of 80-bit instructions. -* -* 7: The trigger will only match against execution of 96-bit instructions. -* -* 8: The trigger will only match against execution of 112-bit instructions. -* -* 9: The trigger will only match against 128-bit memory accesses or -* execution of 128-bit instructions. + * This field contains the 2 low bits of the access size. The high bits come + * from \FcsrMcontrolSizehi. The combined value is interpreted as follows: + * + * 0: The trigger will attempt to match against an access of any size. + * The behavior is only well-defined if $|select|=0$, or if the access + * size is XLEN. + * + * 1: The trigger will only match against 8-bit memory accesses. + * + * 2: The trigger will only match against 16-bit memory accesses or + * execution of 16-bit instructions. + * + * 3: The trigger will only match against 32-bit memory accesses or + * execution of 32-bit instructions. + * + * 4: The trigger will only match against execution of 48-bit instructions. + * + * 5: The trigger will only match against 64-bit memory accesses or + * execution of 64-bit instructions. + * + * 6: The trigger will only match against execution of 80-bit instructions. + * + * 7: The trigger will only match against execution of 96-bit instructions. + * + * 8: The trigger will only match against execution of 112-bit instructions. + * + * 9: The trigger will only match against 128-bit memory accesses or + * execution of 128-bit instructions. + * + * An implementation must support the value of 0, but all other values + * are optional. It is recommended to support triggers for every + * access size the hart supports, as well as for every instruction + * size the hart supports. */ #define CSR_MCONTROL_SIZELO_OFFSET 16 #define CSR_MCONTROL_SIZELO_LENGTH 2 #define CSR_MCONTROL_SIZELO (0x3ULL << CSR_MCONTROL_SIZELO_OFFSET) /* -* The action to take when the trigger fires. The values are explained -* in Table~\ref{tab:action}. + * The action to take when the trigger fires. The values are explained + * in Table~\ref{tab:action}. */ #define CSR_MCONTROL_ACTION_OFFSET 12 #define CSR_MCONTROL_ACTION_LENGTH 4 #define CSR_MCONTROL_ACTION (0xfULL << CSR_MCONTROL_ACTION_OFFSET) /* -* 0: When this trigger matches, the configured action is taken. -* -* 1: While this trigger does not match, it prevents the trigger with -* the next index from matching. -* -* A trigger chain starts on the first trigger with $|chain|=1$ after -* a trigger with $|chain|=0$, or simply on the first trigger if that -* has $|chain|=1$. It ends on the first trigger after that which has -* $|chain|=0$. This final trigger is part of the chain. The action -* on all but the final trigger is ignored. The action on that final -* trigger will be taken if and only if all the triggers in the chain -* match at the same time. -* -* Because \Fchain affects the next trigger, hardware must zero it in -* writes to \Rmcontrol that set \Fdmode to 0 if the next trigger has -* \Fdmode of 1. -* In addition hardware should ignore writes to \Rmcontrol that set -* \Fdmode to 1 if the previous trigger has both \Fdmode of 0 and -* \Fchain of 1. Debuggers must avoid the latter case by checking -* \Fchain on the previous trigger if they're writing \Rmcontrol. -* -* Implementations that wish to limit the maximum length of a trigger -* chain (eg. to meet timing requirements) may do so by zeroing -* \Fchain in writes to \Rmcontrol that would make the chain too long. + * 0: When this trigger matches, the configured action is taken. + * + * 1: While this trigger does not match, it prevents the trigger with + * the next index from matching. + * + * A trigger chain starts on the first trigger with $|chain|=1$ after + * a trigger with $|chain|=0$, or simply on the first trigger if that + * has $|chain|=1$. It ends on the first trigger after that which has + * $|chain|=0$. This final trigger is part of the chain. The action + * on all but the final trigger is ignored. The action on that final + * trigger will be taken if and only if all the triggers in the chain + * match at the same time. + * + * Because \FcsrMcontrolChain affects the next trigger, hardware must zero it in + * writes to \RcsrMcontrol that set \FcsrTdataOneDmode to 0 if the next trigger has + * \FcsrTdataOneDmode of 1. + * In addition hardware should ignore writes to \RcsrMcontrol that set + * \FcsrTdataOneDmode to 1 if the previous trigger has both \FcsrTdataOneDmode of 0 and + * \FcsrMcontrolChain of 1. Debuggers must avoid the latter case by checking + * \FcsrMcontrolChain on the previous trigger if they're writing \RcsrMcontrol. + * + * Implementations that wish to limit the maximum length of a trigger + * chain (eg. to meet timing requirements) may do so by zeroing + * \FcsrMcontrolChain in writes to \RcsrMcontrol that would make the chain too long. */ #define CSR_MCONTROL_CHAIN_OFFSET 11 #define CSR_MCONTROL_CHAIN_LENGTH 1 #define CSR_MCONTROL_CHAIN (0x1ULL << CSR_MCONTROL_CHAIN_OFFSET) /* -* 0: Matches when the value equals \Rtdatatwo. Additionally, if -* \Fselect=0 then it is recommended that the trigger also matches if -* any of the accessed addresses equal \Rtdatatwo. (E.g. on a 32-bit -* read from 0x4000, the following addresses are accessed: 0x4000, -* 0x4001, 0x4002, and 0x4003.) -* -* 1: Matches when the top M bits of the value match the top M bits of -* \Rtdatatwo. M is XLEN-1 minus the index of the least-significant -* bit containing 0 in \Rtdatatwo. -* -* 2: Matches when the value is greater than (unsigned) or equal to -* \Rtdatatwo. -* -* 3: Matches when the value is less than (unsigned) \Rtdatatwo. -* -* 4: Matches when the lower half of the value equals the lower half -* of \Rtdatatwo after the lower half of the value is ANDed with the -* upper half of \Rtdatatwo. -* -* 5: Matches when the upper half of the value equals the lower half -* of \Rtdatatwo after the upper half of the value is ANDed with the -* upper half of \Rtdatatwo. -* -* Other values are reserved for future use. + * 0: Matches when the value equals \RcsrTdataTwo. + * + * 1: Matches when the top M bits of the value match the top M bits of + * \RcsrTdataTwo. M is XLEN-1 minus the index of the least-significant + * bit containing 0 in \RcsrTdataTwo. Debuggers should only write values + * to \RcsrTdataTwo such that M + \FcsrMcontrolMaskmax $\geq$ XLEN, otherwise it's + * undefined on what conditions the trigger will fire. + * + * 2: Matches when the value is greater than (unsigned) or equal to + * \RcsrTdataTwo. + * + * 3: Matches when the value is less than (unsigned) \RcsrTdataTwo. + * + * 4: Matches when the lower half of the value equals the lower half + * of \RcsrTdataTwo after the lower half of the value is ANDed with the + * upper half of \RcsrTdataTwo. + * + * 5: Matches when the upper half of the value equals the lower half + * of \RcsrTdataTwo after the upper half of the value is ANDed with the + * upper half of \RcsrTdataTwo. + * + * 8: Matches when \FcsrMcontrolMatch$=0$ would not match. + * + * 9: Matches when \FcsrMcontrolMatch$=1$ would not match. + * + * 12: Matches when \FcsrMcontrolMatch$=4$ would not match. + * + * 13: Matches when \FcsrMcontrolMatch$=5$ would not match. + * + * Other values are reserved for future use. */ #define CSR_MCONTROL_MATCH_OFFSET 7 #define CSR_MCONTROL_MATCH_LENGTH 4 #define CSR_MCONTROL_MATCH (0xfULL << CSR_MCONTROL_MATCH_OFFSET) /* -* When set, enable this trigger in M-mode. + * When set, enable this trigger in M-mode. */ #define CSR_MCONTROL_M_OFFSET 6 #define CSR_MCONTROL_M_LENGTH 1 #define CSR_MCONTROL_M (0x1ULL << CSR_MCONTROL_M_OFFSET) /* -* When set, enable this trigger in S-mode. + * When set, enable this trigger in S-mode. */ #define CSR_MCONTROL_S_OFFSET 4 #define CSR_MCONTROL_S_LENGTH 1 #define CSR_MCONTROL_S (0x1ULL << CSR_MCONTROL_S_OFFSET) /* -* When set, enable this trigger in U-mode. + * When set, enable this trigger in U-mode. */ #define CSR_MCONTROL_U_OFFSET 3 #define CSR_MCONTROL_U_LENGTH 1 #define CSR_MCONTROL_U (0x1ULL << CSR_MCONTROL_U_OFFSET) /* -* When set, the trigger fires on the virtual address or opcode of an -* instruction that is executed. + * When set, the trigger fires on the virtual address or opcode of an + * instruction that is executed. */ #define CSR_MCONTROL_EXECUTE_OFFSET 2 #define CSR_MCONTROL_EXECUTE_LENGTH 1 #define CSR_MCONTROL_EXECUTE (0x1ULL << CSR_MCONTROL_EXECUTE_OFFSET) /* -* When set, the trigger fires on the virtual address or data of a store. + * When set, the trigger fires on the virtual address or data of any + * store. */ #define CSR_MCONTROL_STORE_OFFSET 1 #define CSR_MCONTROL_STORE_LENGTH 1 #define CSR_MCONTROL_STORE (0x1ULL << CSR_MCONTROL_STORE_OFFSET) /* -* When set, the trigger fires on the virtual address or data of a load. + * When set, the trigger fires on the virtual address or data of any + * load. */ #define CSR_MCONTROL_LOAD_OFFSET 0 #define CSR_MCONTROL_LOAD_LENGTH 1 @@ -652,48 +684,48 @@ #define CSR_ICOUNT_DMODE_LENGTH 1 #define CSR_ICOUNT_DMODE (0x1ULL << CSR_ICOUNT_DMODE_OFFSET) /* -* If this optional bit is implemented, the hardware sets it when this -* trigger matches. The trigger's user can set or clear it at any -* time. It is used to determine which -* trigger(s) matched. If the bit is not implemented, it is always 0 -* and writing it has no effect. + * If this bit is implemented, the hardware sets it when this + * trigger matches. The trigger's user can set or clear it at any + * time. It is used to determine which + * trigger(s) matched. If the bit is not implemented, it is always 0 + * and writing it has no effect. */ #define CSR_ICOUNT_HIT_OFFSET 24 #define CSR_ICOUNT_HIT_LENGTH 1 #define CSR_ICOUNT_HIT (0x1ULL << CSR_ICOUNT_HIT_OFFSET) /* -* When count is decremented to 0, the trigger fires. Instead of -* changing \Fcount from 1 to 0, it is also acceptable for hardware to -* clear \Fm, \Fs, and \Fu. This allows \Fcount to be hard-wired -* to 1 if this register just exists for single step. + * When count is decremented to 0, the trigger fires. Instead of + * changing \FcsrIcountCount from 1 to 0, it is also acceptable for hardware to + * clear \FcsrMcontrolM, \FcsrMcontrolS, and \FcsrMcontrolU. This allows \FcsrIcountCount to be hard-wired + * to 1 if this register just exists for single step. */ #define CSR_ICOUNT_COUNT_OFFSET 10 #define CSR_ICOUNT_COUNT_LENGTH 14 #define CSR_ICOUNT_COUNT (0x3fffULL << CSR_ICOUNT_COUNT_OFFSET) /* -* When set, every instruction completed or exception taken in M-mode decrements \Fcount -* by 1. + * When set, every instruction completed in or trap taken from + * M-mode decrements \FcsrIcountCount by 1. */ #define CSR_ICOUNT_M_OFFSET 9 #define CSR_ICOUNT_M_LENGTH 1 #define CSR_ICOUNT_M (0x1ULL << CSR_ICOUNT_M_OFFSET) /* -* When set, every instruction completed or exception taken in S-mode decrements \Fcount -* by 1. + * When set, every instruction completed in or trap taken from + * S-mode decrements \FcsrIcountCount by 1. */ #define CSR_ICOUNT_S_OFFSET 7 #define CSR_ICOUNT_S_LENGTH 1 #define CSR_ICOUNT_S (0x1ULL << CSR_ICOUNT_S_OFFSET) /* -* When set, every instruction completed or exception taken in U-mode decrements \Fcount -* by 1. + * When set, every instruction completed in or trap taken from + * U-mode decrements \FcsrIcountCount by 1. */ #define CSR_ICOUNT_U_OFFSET 6 #define CSR_ICOUNT_U_LENGTH 1 #define CSR_ICOUNT_U (0x1ULL << CSR_ICOUNT_U_OFFSET) /* -* The action to take when the trigger fires. The values are explained -* in Table~\ref{tab:action}. + * The action to take when the trigger fires. The values are explained + * in Table~\ref{tab:action}. */ #define CSR_ICOUNT_ACTION_OFFSET 0 #define CSR_ICOUNT_ACTION_LENGTH 6 @@ -706,39 +738,39 @@ #define CSR_ITRIGGER_DMODE_LENGTH 1 #define CSR_ITRIGGER_DMODE (0x1ULL << CSR_ITRIGGER_DMODE_OFFSET) /* -* If this optional bit is implemented, the hardware sets it when this -* trigger matches. The trigger's user can set or clear it at any -* time. It is used to determine which -* trigger(s) matched. If the bit is not implemented, it is always 0 -* and writing it has no effect. + * If this bit is implemented, the hardware sets it when this + * trigger matches. The trigger's user can set or clear it at any + * time. It is used to determine which + * trigger(s) matched. If the bit is not implemented, it is always 0 + * and writing it has no effect. */ #define CSR_ITRIGGER_HIT_OFFSET (XLEN-6) #define CSR_ITRIGGER_HIT_LENGTH 1 #define CSR_ITRIGGER_HIT (0x1ULL << CSR_ITRIGGER_HIT_OFFSET) /* -* When set, enable this trigger for interrupts that are taken from M -* mode. + * When set, enable this trigger for interrupts that are taken from M + * mode. */ #define CSR_ITRIGGER_M_OFFSET 9 #define CSR_ITRIGGER_M_LENGTH 1 #define CSR_ITRIGGER_M (0x1ULL << CSR_ITRIGGER_M_OFFSET) /* -* When set, enable this trigger for interrupts that are taken from S -* mode. + * When set, enable this trigger for interrupts that are taken from S + * mode. */ #define CSR_ITRIGGER_S_OFFSET 7 #define CSR_ITRIGGER_S_LENGTH 1 #define CSR_ITRIGGER_S (0x1ULL << CSR_ITRIGGER_S_OFFSET) /* -* When set, enable this trigger for interrupts that are taken from U -* mode. + * When set, enable this trigger for interrupts that are taken from U + * mode. */ #define CSR_ITRIGGER_U_OFFSET 6 #define CSR_ITRIGGER_U_LENGTH 1 #define CSR_ITRIGGER_U (0x1ULL << CSR_ITRIGGER_U_OFFSET) /* -* The action to take when the trigger fires. The values are explained -* in Table~\ref{tab:action}. + * The action to take when the trigger fires. The values are explained + * in Table~\ref{tab:action}. */ #define CSR_ITRIGGER_ACTION_OFFSET 0 #define CSR_ITRIGGER_ACTION_LENGTH 6 @@ -751,81 +783,85 @@ #define CSR_ETRIGGER_DMODE_LENGTH 1 #define CSR_ETRIGGER_DMODE (0x1ULL << CSR_ETRIGGER_DMODE_OFFSET) /* -* If this optional bit is implemented, the hardware sets it when this -* trigger matches. The trigger's user can set or clear it at any -* time. It is used to determine which -* trigger(s) matched. If the bit is not implemented, it is always 0 -* and writing it has no effect. + * If this bit is implemented, the hardware sets it when this + * trigger matches. The trigger's user can set or clear it at any + * time. It is used to determine which + * trigger(s) matched. If the bit is not implemented, it is always 0 + * and writing it has no effect. */ #define CSR_ETRIGGER_HIT_OFFSET (XLEN-6) #define CSR_ETRIGGER_HIT_LENGTH 1 #define CSR_ETRIGGER_HIT (0x1ULL << CSR_ETRIGGER_HIT_OFFSET) /* -* When this optional bit is set, non-maskable interrupts cause this -* trigger to fire, regardless of the values of \Fm, \Fs, and \Fu. + * When set, non-maskable interrupts cause this + * trigger to fire, regardless of the values of \FcsrMcontrolM, \FcsrMcontrolS, and \FcsrMcontrolU. */ #define CSR_ETRIGGER_NMI_OFFSET 10 #define CSR_ETRIGGER_NMI_LENGTH 1 #define CSR_ETRIGGER_NMI (0x1ULL << CSR_ETRIGGER_NMI_OFFSET) /* -* When set, enable this trigger for exceptions that are taken from M -* mode. + * When set, enable this trigger for exceptions that are taken from M + * mode. */ #define CSR_ETRIGGER_M_OFFSET 9 #define CSR_ETRIGGER_M_LENGTH 1 #define CSR_ETRIGGER_M (0x1ULL << CSR_ETRIGGER_M_OFFSET) /* -* When set, enable this trigger for exceptions that are taken from S -* mode. + * When set, enable this trigger for exceptions that are taken from S + * mode. */ #define CSR_ETRIGGER_S_OFFSET 7 #define CSR_ETRIGGER_S_LENGTH 1 #define CSR_ETRIGGER_S (0x1ULL << CSR_ETRIGGER_S_OFFSET) /* -* When set, enable this trigger for exceptions that are taken from U -* mode. + * When set, enable this trigger for exceptions that are taken from U + * mode. */ #define CSR_ETRIGGER_U_OFFSET 6 #define CSR_ETRIGGER_U_LENGTH 1 #define CSR_ETRIGGER_U (0x1ULL << CSR_ETRIGGER_U_OFFSET) /* -* The action to take when the trigger fires. The values are explained -* in Table~\ref{tab:action}. + * The action to take when the trigger fires. The values are explained + * in Table~\ref{tab:action}. */ #define CSR_ETRIGGER_ACTION_OFFSET 0 #define CSR_ETRIGGER_ACTION_LENGTH 6 #define CSR_ETRIGGER_ACTION (0x3fULL << CSR_ETRIGGER_ACTION_OFFSET) #define CSR_TEXTRA32 0x7a3 /* -* Data used together with \Fmselect. + * Data used together with \FcsrTextraThirtytwoMselect. */ #define CSR_TEXTRA32_MVALUE_OFFSET 26 #define CSR_TEXTRA32_MVALUE_LENGTH 6 #define CSR_TEXTRA32_MVALUE (0x3fU << CSR_TEXTRA32_MVALUE_OFFSET) /* -* 0: Ignore \Fmvalue. -* -* 1: This trigger will only match if the low bits of -* \Rmcontext equal \Fmvalue. + * 0: Ignore \FcsrTextraThirtytwoMvalue. + * + * 1: This trigger will only match if the low bits of + * \RcsrMcontext equal \FcsrTextraThirtytwoMvalue. */ #define CSR_TEXTRA32_MSELECT_OFFSET 25 #define CSR_TEXTRA32_MSELECT_LENGTH 1 #define CSR_TEXTRA32_MSELECT (0x1U << CSR_TEXTRA32_MSELECT_OFFSET) /* -* Data used together with \Fsselect. + * Data used together with \FcsrTextraThirtytwoSselect. + * + * This field should be tied to 0 when S-mode is not supported. */ #define CSR_TEXTRA32_SVALUE_OFFSET 2 #define CSR_TEXTRA32_SVALUE_LENGTH 16 #define CSR_TEXTRA32_SVALUE (0xffffU << CSR_TEXTRA32_SVALUE_OFFSET) /* -* 0: Ignore \Fsvalue. -* -* 1: This trigger will only match if the low bits of -* \Rscontext equal \Fsvalue. -* -* 2: This trigger will only match if \Fasid in \Rsatp -* equals the lower ASIDMAX (defined in the Privileged Spec) bits of -* \Fsvalue. + * 0: Ignore \FcsrTextraThirtytwoSvalue. + * + * 1: This trigger will only match if the low bits of + * \RcsrScontext equal \FcsrTextraThirtytwoSvalue. + * + * 2: This trigger will only match if \Fasid in \Rsatp + * equals the lower ASIDMAX (defined in the Privileged Spec) bits of + * \FcsrTextraThirtytwoSvalue. + * + * This field should be tied to 0 when S-mode is not supported. */ #define CSR_TEXTRA32_SSELECT_OFFSET 0 #define CSR_TEXTRA32_SSELECT_LENGTH 2 @@ -843,906 +879,952 @@ #define CSR_TEXTRA64_SSELECT_OFFSET 0 #define CSR_TEXTRA64_SSELECT_LENGTH 2 #define CSR_TEXTRA64_SSELECT (0x3ULL << CSR_TEXTRA64_SSELECT_OFFSET) -#define DMI_DMSTATUS 0x11 +#define DM_DMSTATUS 0x11 /* -* If 1, then there is an implicit {\tt ebreak} instruction at the -* non-existent word immediately after the Program Buffer. This saves -* the debugger from having to write the {\tt ebreak} itself, and -* allows the Program Buffer to be one word smaller. -* -* This must be 1 when \Fprogbufsize is 1. + * If 1, then there is an implicit {\tt ebreak} instruction at the + * non-existent word immediately after the Program Buffer. This saves + * the debugger from having to write the {\tt ebreak} itself, and + * allows the Program Buffer to be one word smaller. + * + * This must be 1 when \FdmAbstractcsProgbufsize is 1. */ -#define DMI_DMSTATUS_IMPEBREAK_OFFSET 22 -#define DMI_DMSTATUS_IMPEBREAK_LENGTH 1 -#define DMI_DMSTATUS_IMPEBREAK (0x1U << DMI_DMSTATUS_IMPEBREAK_OFFSET) +#define DM_DMSTATUS_IMPEBREAK_OFFSET 22 +#define DM_DMSTATUS_IMPEBREAK_LENGTH 1 +#define DM_DMSTATUS_IMPEBREAK (0x1U << DM_DMSTATUS_IMPEBREAK_OFFSET) /* -* This field is 1 when all currently selected harts have been reset -* and reset has not been acknowledged for any of them. + * This field is 1 when all currently selected harts have been reset + * and reset has not been acknowledged for any of them. */ -#define DMI_DMSTATUS_ALLHAVERESET_OFFSET 19 -#define DMI_DMSTATUS_ALLHAVERESET_LENGTH 1 -#define DMI_DMSTATUS_ALLHAVERESET (0x1U << DMI_DMSTATUS_ALLHAVERESET_OFFSET) +#define DM_DMSTATUS_ALLHAVERESET_OFFSET 19 +#define DM_DMSTATUS_ALLHAVERESET_LENGTH 1 +#define DM_DMSTATUS_ALLHAVERESET (0x1U << DM_DMSTATUS_ALLHAVERESET_OFFSET) /* -* This field is 1 when at least one currently selected hart has been -* reset and reset has not been acknowledged for that hart. + * This field is 1 when at least one currently selected hart has been + * reset and reset has not been acknowledged for that hart. */ -#define DMI_DMSTATUS_ANYHAVERESET_OFFSET 18 -#define DMI_DMSTATUS_ANYHAVERESET_LENGTH 1 -#define DMI_DMSTATUS_ANYHAVERESET (0x1U << DMI_DMSTATUS_ANYHAVERESET_OFFSET) +#define DM_DMSTATUS_ANYHAVERESET_OFFSET 18 +#define DM_DMSTATUS_ANYHAVERESET_LENGTH 1 +#define DM_DMSTATUS_ANYHAVERESET (0x1U << DM_DMSTATUS_ANYHAVERESET_OFFSET) /* -* This field is 1 when all currently selected harts have acknowledged -* their last resume request. + * This field is 1 when all currently selected harts have acknowledged + * their last resume request. */ -#define DMI_DMSTATUS_ALLRESUMEACK_OFFSET 17 -#define DMI_DMSTATUS_ALLRESUMEACK_LENGTH 1 -#define DMI_DMSTATUS_ALLRESUMEACK (0x1U << DMI_DMSTATUS_ALLRESUMEACK_OFFSET) +#define DM_DMSTATUS_ALLRESUMEACK_OFFSET 17 +#define DM_DMSTATUS_ALLRESUMEACK_LENGTH 1 +#define DM_DMSTATUS_ALLRESUMEACK (0x1U << DM_DMSTATUS_ALLRESUMEACK_OFFSET) /* -* This field is 1 when any currently selected hart has acknowledged -* its last resume request. + * This field is 1 when any currently selected hart has acknowledged + * its last resume request. */ -#define DMI_DMSTATUS_ANYRESUMEACK_OFFSET 16 -#define DMI_DMSTATUS_ANYRESUMEACK_LENGTH 1 -#define DMI_DMSTATUS_ANYRESUMEACK (0x1U << DMI_DMSTATUS_ANYRESUMEACK_OFFSET) +#define DM_DMSTATUS_ANYRESUMEACK_OFFSET 16 +#define DM_DMSTATUS_ANYRESUMEACK_LENGTH 1 +#define DM_DMSTATUS_ANYRESUMEACK (0x1U << DM_DMSTATUS_ANYRESUMEACK_OFFSET) /* -* This field is 1 when all currently selected harts do not exist in -* this platform. - */ -#define DMI_DMSTATUS_ALLNONEXISTENT_OFFSET 15 -#define DMI_DMSTATUS_ALLNONEXISTENT_LENGTH 1 -#define DMI_DMSTATUS_ALLNONEXISTENT (0x1U << DMI_DMSTATUS_ALLNONEXISTENT_OFFSET) -/* -* This field is 1 when any currently selected hart does not exist in -* this platform. - */ -#define DMI_DMSTATUS_ANYNONEXISTENT_OFFSET 14 -#define DMI_DMSTATUS_ANYNONEXISTENT_LENGTH 1 -#define DMI_DMSTATUS_ANYNONEXISTENT (0x1U << DMI_DMSTATUS_ANYNONEXISTENT_OFFSET) -/* -* This field is 1 when all currently selected harts are unavailable. - */ -#define DMI_DMSTATUS_ALLUNAVAIL_OFFSET 13 -#define DMI_DMSTATUS_ALLUNAVAIL_LENGTH 1 -#define DMI_DMSTATUS_ALLUNAVAIL (0x1U << DMI_DMSTATUS_ALLUNAVAIL_OFFSET) -/* -* This field is 1 when any currently selected hart is unavailable. - */ -#define DMI_DMSTATUS_ANYUNAVAIL_OFFSET 12 -#define DMI_DMSTATUS_ANYUNAVAIL_LENGTH 1 -#define DMI_DMSTATUS_ANYUNAVAIL (0x1U << DMI_DMSTATUS_ANYUNAVAIL_OFFSET) -/* -* This field is 1 when all currently selected harts are running. - */ -#define DMI_DMSTATUS_ALLRUNNING_OFFSET 11 -#define DMI_DMSTATUS_ALLRUNNING_LENGTH 1 -#define DMI_DMSTATUS_ALLRUNNING (0x1U << DMI_DMSTATUS_ALLRUNNING_OFFSET) -/* -* This field is 1 when any currently selected hart is running. - */ -#define DMI_DMSTATUS_ANYRUNNING_OFFSET 10 -#define DMI_DMSTATUS_ANYRUNNING_LENGTH 1 -#define DMI_DMSTATUS_ANYRUNNING (0x1U << DMI_DMSTATUS_ANYRUNNING_OFFSET) -/* -* This field is 1 when all currently selected harts are halted. - */ -#define DMI_DMSTATUS_ALLHALTED_OFFSET 9 -#define DMI_DMSTATUS_ALLHALTED_LENGTH 1 -#define DMI_DMSTATUS_ALLHALTED (0x1U << DMI_DMSTATUS_ALLHALTED_OFFSET) -/* -* This field is 1 when any currently selected hart is halted. - */ -#define DMI_DMSTATUS_ANYHALTED_OFFSET 8 -#define DMI_DMSTATUS_ANYHALTED_LENGTH 1 -#define DMI_DMSTATUS_ANYHALTED (0x1U << DMI_DMSTATUS_ANYHALTED_OFFSET) -/* -* 0: Authentication is required before using the DM. -* -* 1: The authentication check has passed. -* -* On components that don't implement authentication, this bit must be -* preset as 1. - */ -#define DMI_DMSTATUS_AUTHENTICATED_OFFSET 7 -#define DMI_DMSTATUS_AUTHENTICATED_LENGTH 1 -#define DMI_DMSTATUS_AUTHENTICATED (0x1U << DMI_DMSTATUS_AUTHENTICATED_OFFSET) -/* -* 0: The authentication module is ready to process the next -* read/write to \Rauthdata. -* -* 1: The authentication module is busy. Accessing \Rauthdata results -* in unspecified behavior. -* -* \Fauthbusy only becomes set in immediate response to an access to -* \Rauthdata. - */ -#define DMI_DMSTATUS_AUTHBUSY_OFFSET 6 -#define DMI_DMSTATUS_AUTHBUSY_LENGTH 1 -#define DMI_DMSTATUS_AUTHBUSY (0x1U << DMI_DMSTATUS_AUTHBUSY_OFFSET) -/* -* 1 if this Debug Module supports halt-on-reset functionality -* controllable by the \Fsetresethaltreq and \Fclrresethaltreq bits. -* 0 otherwise. - */ -#define DMI_DMSTATUS_HASRESETHALTREQ_OFFSET 5 -#define DMI_DMSTATUS_HASRESETHALTREQ_LENGTH 1 -#define DMI_DMSTATUS_HASRESETHALTREQ (0x1U << DMI_DMSTATUS_HASRESETHALTREQ_OFFSET) -/* -* 0: \Rconfstrptrzero--\Rconfstrptrthree hold information which -* is not relevant to the configuration string. -* -* 1: \Rconfstrptrzero--\Rconfstrptrthree hold the address of the -* configuration string. - */ -#define DMI_DMSTATUS_CONFSTRPTRVALID_OFFSET 4 -#define DMI_DMSTATUS_CONFSTRPTRVALID_LENGTH 1 -#define DMI_DMSTATUS_CONFSTRPTRVALID (0x1U << DMI_DMSTATUS_CONFSTRPTRVALID_OFFSET) -/* -* 0: There is no Debug Module present. -* -* 1: There is a Debug Module and it conforms to version 0.11 of this -* specification. -* -* 2: There is a Debug Module and it conforms to version 0.13 of this -* specification. -* -* 15: There is a Debug Module but it does not conform to any -* available version of this spec. - */ -#define DMI_DMSTATUS_VERSION_OFFSET 0 -#define DMI_DMSTATUS_VERSION_LENGTH 4 -#define DMI_DMSTATUS_VERSION (0xfU << DMI_DMSTATUS_VERSION_OFFSET) -#define DMI_DMCONTROL 0x10 -/* -* Writing 0 clears the halt request bit for all currently selected -* harts. This may cancel outstanding halt requests for those harts. -* -* Writing 1 sets the halt request bit for all currently selected -* harts. Running harts will halt whenever their halt request bit is -* set. -* -* Writes apply to the new value of \Fhartsel and \Fhasel. - */ -#define DMI_DMCONTROL_HALTREQ_OFFSET 31 -#define DMI_DMCONTROL_HALTREQ_LENGTH 1 -#define DMI_DMCONTROL_HALTREQ (0x1U << DMI_DMCONTROL_HALTREQ_OFFSET) -/* -* Writing 1 causes the currently selected harts to resume once, if -* they are halted when the write occurs. It also clears the resume -* ack bit for those harts. -* -* \Fresumereq is ignored if \Fhaltreq is set. -* -* Writes apply to the new value of \Fhartsel and \Fhasel. - */ -#define DMI_DMCONTROL_RESUMEREQ_OFFSET 30 -#define DMI_DMCONTROL_RESUMEREQ_LENGTH 1 -#define DMI_DMCONTROL_RESUMEREQ (0x1U << DMI_DMCONTROL_RESUMEREQ_OFFSET) -/* -* This optional field writes the reset bit for all the currently -* selected harts. To perform a reset the debugger writes 1, and then -* writes 0 to deassert the reset signal. -* -* While this bit is 1, the debugger must not change which harts are -* selected. -* -* If this feature is not implemented, the bit always stays 0, so -* after writing 1 the debugger can read the register back to see if -* the feature is supported. -* -* Writes apply to the new value of \Fhartsel and \Fhasel. - */ -#define DMI_DMCONTROL_HARTRESET_OFFSET 29 -#define DMI_DMCONTROL_HARTRESET_LENGTH 1 -#define DMI_DMCONTROL_HARTRESET (0x1U << DMI_DMCONTROL_HARTRESET_OFFSET) -/* -* 0: No effect. -* -* 1: Clears {\tt havereset} for any selected harts. -* -* Writes apply to the new value of \Fhartsel and \Fhasel. - */ -#define DMI_DMCONTROL_ACKHAVERESET_OFFSET 28 -#define DMI_DMCONTROL_ACKHAVERESET_LENGTH 1 -#define DMI_DMCONTROL_ACKHAVERESET (0x1U << DMI_DMCONTROL_ACKHAVERESET_OFFSET) -/* -* Selects the definition of currently selected harts. -* -* 0: There is a single currently selected hart, that is selected by \Fhartsel. -* -* 1: There may be multiple currently selected harts -- the hart -* selected by \Fhartsel, plus those selected by the hart array mask -* register. -* -* An implementation which does not implement the hart array mask register -* must tie this field to 0. A debugger which wishes to use the hart array -* mask register feature should set this bit and read back to see if the functionality -* is supported. - */ -#define DMI_DMCONTROL_HASEL_OFFSET 26 -#define DMI_DMCONTROL_HASEL_LENGTH 1 -#define DMI_DMCONTROL_HASEL (0x1U << DMI_DMCONTROL_HASEL_OFFSET) -/* -* The low 10 bits of \Fhartsel: the DM-specific index of the hart to -* select. This hart is always part of the currently selected harts. - */ -#define DMI_DMCONTROL_HARTSELLO_OFFSET 16 -#define DMI_DMCONTROL_HARTSELLO_LENGTH 10 -#define DMI_DMCONTROL_HARTSELLO (0x3ffU << DMI_DMCONTROL_HARTSELLO_OFFSET) -/* -* The high 10 bits of \Fhartsel: the DM-specific index of the hart to -* select. This hart is always part of the currently selected harts. - */ -#define DMI_DMCONTROL_HARTSELHI_OFFSET 6 -#define DMI_DMCONTROL_HARTSELHI_LENGTH 10 -#define DMI_DMCONTROL_HARTSELHI (0x3ffU << DMI_DMCONTROL_HARTSELHI_OFFSET) -/* -* This optional field writes the halt-on-reset request bit for all -* currently selected harts, unless \Fclrresethaltreq is -* simultaneously set to 1. -* When set to 1, each selected hart will halt upon the next deassertion -* of its reset. The halt-on-reset request bit is not automatically -* cleared. The debugger must write to \Fclrresethaltreq to clear it. -* -* Writes apply to the new value of \Fhartsel and \Fhasel. -* -* If \Fhasresethaltreq is 0, this field is not implemented. - */ -#define DMI_DMCONTROL_SETRESETHALTREQ_OFFSET 3 -#define DMI_DMCONTROL_SETRESETHALTREQ_LENGTH 1 -#define DMI_DMCONTROL_SETRESETHALTREQ (0x1U << DMI_DMCONTROL_SETRESETHALTREQ_OFFSET) -/* -* This optional field clears the halt-on-reset request bit for all -* currently selected harts. -* -* Writes apply to the new value of \Fhartsel and \Fhasel. - */ -#define DMI_DMCONTROL_CLRRESETHALTREQ_OFFSET 2 -#define DMI_DMCONTROL_CLRRESETHALTREQ_LENGTH 1 -#define DMI_DMCONTROL_CLRRESETHALTREQ (0x1U << DMI_DMCONTROL_CLRRESETHALTREQ_OFFSET) -/* -* This bit controls the reset signal from the DM to the rest of the -* system. The signal should reset every part of the system, including -* every hart, except for the DM and any logic required to access the -* DM. -* To perform a system reset the debugger writes 1, -* and then writes 0 -* to deassert the reset. - */ -#define DMI_DMCONTROL_NDMRESET_OFFSET 1 -#define DMI_DMCONTROL_NDMRESET_LENGTH 1 -#define DMI_DMCONTROL_NDMRESET (0x1U << DMI_DMCONTROL_NDMRESET_OFFSET) -/* -* This bit serves as a reset signal for the Debug Module itself. -* -* 0: The module's state, including authentication mechanism, -* takes its reset values (the \Fdmactive bit is the only bit which can -* be written to something other than its reset value). Any accesses -* to the module may fail. Specifically, \Fversion may not return -* correct data. -* -* 1: The module functions normally. -* -* No other mechanism should exist that may result in resetting the -* Debug Module after power up, with the possible (but not -* recommended) exception of a global reset signal that resets the -* entire platform. -* -* A debugger may pulse this bit low to get the Debug Module into a -* known state. -* -* Implementations may pay attention to this bit to further aid -* debugging, for example by preventing the Debug Module from being -* power gated while debugging is active. -* -* For forward compatibility, \Fversion will always be readable when -* \Fdmactive is 1. - */ -#define DMI_DMCONTROL_DMACTIVE_OFFSET 0 -#define DMI_DMCONTROL_DMACTIVE_LENGTH 1 -#define DMI_DMCONTROL_DMACTIVE (0x1U << DMI_DMCONTROL_DMACTIVE_OFFSET) -#define DMI_HARTINFO 0x12 -/* -* Number of {\tt dscratch} registers available for the debugger -* to use during program buffer execution, starting from \Rdscratchzero. -* The debugger can make no assumptions about the contents of these -* registers between commands. - */ -#define DMI_HARTINFO_NSCRATCH_OFFSET 20 -#define DMI_HARTINFO_NSCRATCH_LENGTH 4 -#define DMI_HARTINFO_NSCRATCH (0xfU << DMI_HARTINFO_NSCRATCH_OFFSET) -/* -* 0: The {\tt data} registers are shadowed in the hart by CSRs. -* Each CSR is DXLEN bits in size, and corresponds -* to a single argument, per Table~\ref{tab:datareg}. -* -* 1: The {\tt data} registers are shadowed in the hart's memory map. -* Each register takes up 4 bytes in the memory map. - */ -#define DMI_HARTINFO_DATAACCESS_OFFSET 16 -#define DMI_HARTINFO_DATAACCESS_LENGTH 1 -#define DMI_HARTINFO_DATAACCESS (0x1U << DMI_HARTINFO_DATAACCESS_OFFSET) -/* -* If \Fdataaccess is 0: Number of CSRs dedicated to -* shadowing the {\tt data} registers. -* -* If \Fdataaccess is 1: Number of 32-bit words in the memory map -* dedicated to shadowing the {\tt data} registers. -* -* Since there are at most 12 {\tt data} registers, the value in this -* register must be 12 or smaller. - */ -#define DMI_HARTINFO_DATASIZE_OFFSET 12 -#define DMI_HARTINFO_DATASIZE_LENGTH 4 -#define DMI_HARTINFO_DATASIZE (0xfU << DMI_HARTINFO_DATASIZE_OFFSET) -/* -* If \Fdataaccess is 0: The number of the first CSR dedicated to -* shadowing the {\tt data} registers. -* -* If \Fdataaccess is 1: Signed address of RAM where the {\tt data} -* registers are shadowed, to be used to access relative to \Rzero. - */ -#define DMI_HARTINFO_DATAADDR_OFFSET 0 -#define DMI_HARTINFO_DATAADDR_LENGTH 12 -#define DMI_HARTINFO_DATAADDR (0xfffU << DMI_HARTINFO_DATAADDR_OFFSET) -#define DMI_HAWINDOWSEL 0x14 -/* -* The high bits of this field may be tied to 0, depending on how large -* the array mask register is. E.g.\ on a system with 48 harts only bit 0 -* of this field may actually be writable. - */ -#define DMI_HAWINDOWSEL_HAWINDOWSEL_OFFSET 0 -#define DMI_HAWINDOWSEL_HAWINDOWSEL_LENGTH 15 -#define DMI_HAWINDOWSEL_HAWINDOWSEL (0x7fffU << DMI_HAWINDOWSEL_HAWINDOWSEL_OFFSET) -#define DMI_HAWINDOW 0x15 -#define DMI_HAWINDOW_MASKDATA_OFFSET 0 -#define DMI_HAWINDOW_MASKDATA_LENGTH 32 -#define DMI_HAWINDOW_MASKDATA (0xffffffffU << DMI_HAWINDOW_MASKDATA_OFFSET) -#define DMI_ABSTRACTCS 0x16 -/* -* Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 16. - */ -#define DMI_ABSTRACTCS_PROGBUFSIZE_OFFSET 24 -#define DMI_ABSTRACTCS_PROGBUFSIZE_LENGTH 5 -#define DMI_ABSTRACTCS_PROGBUFSIZE (0x1fU << DMI_ABSTRACTCS_PROGBUFSIZE_OFFSET) -/* -* 1: An abstract command is currently being executed. -* -* This bit is set as soon as \Rcommand is written, and is -* not cleared until that command has completed. - */ -#define DMI_ABSTRACTCS_BUSY_OFFSET 12 -#define DMI_ABSTRACTCS_BUSY_LENGTH 1 -#define DMI_ABSTRACTCS_BUSY (0x1U << DMI_ABSTRACTCS_BUSY_OFFSET) -/* -* Gets set if an abstract command fails. The bits in this field remain set until -* they are cleared by writing 1 to them. No abstract command is -* started until the value is reset to 0. -* -* This field only contains a valid value if \Fbusy is 0. -* -* 0 (none): No error. -* -* 1 (busy): An abstract command was executing while \Rcommand, -* \Rabstractcs, or \Rabstractauto was written, or when one -* of the {\tt data} or {\tt progbuf} registers was read or written. -* This status is only written if \Fcmderr contains 0. -* -* 2 (not supported): The requested command is not supported, -* regardless of whether the hart is running or not. -* -* 3 (exception): An exception occurred while executing the command -* (e.g.\ while executing the Program Buffer). -* -* 4 (halt/resume): The abstract command couldn't execute because the -* hart wasn't in the required state (running/halted), or unavailable. -* -* 5 (bus): The abstract command failed due to a bus error (e.g.\ -* alignment, access size, or timeout). -* -* 7 (other): The command failed for another reason. - */ -#define DMI_ABSTRACTCS_CMDERR_OFFSET 8 -#define DMI_ABSTRACTCS_CMDERR_LENGTH 3 -#define DMI_ABSTRACTCS_CMDERR (0x7U << DMI_ABSTRACTCS_CMDERR_OFFSET) -/* -* Number of {\tt data} registers that are implemented as part of the -* abstract command interface. Valid sizes are 1 -- 12. - */ -#define DMI_ABSTRACTCS_DATACOUNT_OFFSET 0 -#define DMI_ABSTRACTCS_DATACOUNT_LENGTH 4 -#define DMI_ABSTRACTCS_DATACOUNT (0xfU << DMI_ABSTRACTCS_DATACOUNT_OFFSET) -#define DMI_COMMAND 0x17 -/* -* The type determines the overall functionality of this -* abstract command. - */ -#define DMI_COMMAND_CMDTYPE_OFFSET 24 -#define DMI_COMMAND_CMDTYPE_LENGTH 8 -#define DMI_COMMAND_CMDTYPE (0xffU << DMI_COMMAND_CMDTYPE_OFFSET) -/* -* This field is interpreted in a command-specific manner, -* described for each abstract command. - */ -#define DMI_COMMAND_CONTROL_OFFSET 0 -#define DMI_COMMAND_CONTROL_LENGTH 24 -#define DMI_COMMAND_CONTROL (0xffffffU << DMI_COMMAND_CONTROL_OFFSET) -#define DMI_ABSTRACTAUTO 0x18 -/* -* When a bit in this field is 1, read or write accesses to the -* corresponding {\tt progbuf} word cause the command in \Rcommand to -* be executed again. - */ -#define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET 16 -#define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_LENGTH 16 -#define DMI_ABSTRACTAUTO_AUTOEXECPROGBUF (0xffffU << DMI_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET) -/* -* When a bit in this field is 1, read or write accesses to the -* corresponding {\tt data} word cause the command in \Rcommand to be -* executed again. - */ -#define DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET 0 -#define DMI_ABSTRACTAUTO_AUTOEXECDATA_LENGTH 12 -#define DMI_ABSTRACTAUTO_AUTOEXECDATA (0xfffU << DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET) -#define DMI_CONFSTRPTR0 0x19 -#define DMI_CONFSTRPTR0_ADDR_OFFSET 0 -#define DMI_CONFSTRPTR0_ADDR_LENGTH 32 -#define DMI_CONFSTRPTR0_ADDR (0xffffffffU << DMI_CONFSTRPTR0_ADDR_OFFSET) -#define DMI_CONFSTRPTR1 0x1a -#define DMI_CONFSTRPTR2 0x1b -#define DMI_CONFSTRPTR3 0x1c -#define DMI_NEXTDM 0x1d -#define DMI_NEXTDM_ADDR_OFFSET 0 -#define DMI_NEXTDM_ADDR_LENGTH 32 -#define DMI_NEXTDM_ADDR (0xffffffffU << DMI_NEXTDM_ADDR_OFFSET) -#define DMI_DATA0 0x04 -#define DMI_DATA0_DATA_OFFSET 0 -#define DMI_DATA0_DATA_LENGTH 32 -#define DMI_DATA0_DATA (0xffffffffU << DMI_DATA0_DATA_OFFSET) -#define DMI_DATA11 0x0f -#define DMI_PROGBUF0 0x20 -#define DMI_PROGBUF0_DATA_OFFSET 0 -#define DMI_PROGBUF0_DATA_LENGTH 32 -#define DMI_PROGBUF0_DATA (0xffffffffU << DMI_PROGBUF0_DATA_OFFSET) -#define DMI_PROGBUF15 0x2f -#define DMI_AUTHDATA 0x30 -#define DMI_AUTHDATA_DATA_OFFSET 0 -#define DMI_AUTHDATA_DATA_LENGTH 32 -#define DMI_AUTHDATA_DATA (0xffffffffU << DMI_AUTHDATA_DATA_OFFSET) -#define DMI_DMCS2 0x32 -/* -* This field contains the currently selected external trigger. -* -* If a non-existent trigger value is written here, the hardware will -* change it to a valid one or 0 if no external triggers exist. - */ -#define DMI_DMCS2_EXTTRIGGER_OFFSET 7 -#define DMI_DMCS2_EXTTRIGGER_LENGTH 4 -#define DMI_DMCS2_EXTTRIGGER (0xfU << DMI_DMCS2_EXTTRIGGER_OFFSET) -/* -* When \Fhgselect is 0, contains the halt group of the hart -* specified by \Fhartsel. -* -* When \Fhgselect is 1, contains the halt group of the external -* trigger selected by \Fexttrigger. -* -* Writes only have an effect if \Fhgwrite is also written 1. -* -* An implementation may tie any number of upper bits in this field to -* 0. If halt groups aren't implemented, then this entire field -* is 0. - */ -#define DMI_DMCS2_HALTGROUP_OFFSET 2 -#define DMI_DMCS2_HALTGROUP_LENGTH 5 -#define DMI_DMCS2_HALTGROUP (0x1fU << DMI_DMCS2_HALTGROUP_OFFSET) -/* -* When \Fhgselect is 0, writing 1 changes the halt group of all -* selected harts to the value written to \Fhaltgroup. -* -* When \Fhgselect is 1, writing 1 changes the halt group of the -* external trigger selected by \Fexttrigger to the value written to -* \Fhaltgroup. -* -* Writing 0 has no effect. - */ -#define DMI_DMCS2_HGWRITE_OFFSET 1 -#define DMI_DMCS2_HGWRITE_LENGTH 1 -#define DMI_DMCS2_HGWRITE (0x1U << DMI_DMCS2_HGWRITE_OFFSET) -/* -* 0: Operate on harts. -* -* 1: Operate on external triggers. -* -* If there are no external triggers, this field must be tied to 0. - */ -#define DMI_DMCS2_HGSELECT_OFFSET 0 -#define DMI_DMCS2_HGSELECT_LENGTH 1 -#define DMI_DMCS2_HGSELECT (0x1U << DMI_DMCS2_HGSELECT_OFFSET) -#define DMI_HALTSUM0 0x40 -#define DMI_HALTSUM0_HALTSUM0_OFFSET 0 -#define DMI_HALTSUM0_HALTSUM0_LENGTH 32 -#define DMI_HALTSUM0_HALTSUM0 (0xffffffffU << DMI_HALTSUM0_HALTSUM0_OFFSET) -#define DMI_HALTSUM1 0x13 -#define DMI_HALTSUM1_HALTSUM1_OFFSET 0 -#define DMI_HALTSUM1_HALTSUM1_LENGTH 32 -#define DMI_HALTSUM1_HALTSUM1 (0xffffffffU << DMI_HALTSUM1_HALTSUM1_OFFSET) -#define DMI_HALTSUM2 0x34 -#define DMI_HALTSUM2_HALTSUM2_OFFSET 0 -#define DMI_HALTSUM2_HALTSUM2_LENGTH 32 -#define DMI_HALTSUM2_HALTSUM2 (0xffffffffU << DMI_HALTSUM2_HALTSUM2_OFFSET) -#define DMI_HALTSUM3 0x35 -#define DMI_HALTSUM3_HALTSUM3_OFFSET 0 -#define DMI_HALTSUM3_HALTSUM3_LENGTH 32 -#define DMI_HALTSUM3_HALTSUM3 (0xffffffffU << DMI_HALTSUM3_HALTSUM3_OFFSET) -#define DMI_SBCS 0x38 -/* -* 0: The System Bus interface conforms to mainline drafts of this -* spec older than 1 January, 2018. -* -* 1: The System Bus interface conforms to this version of the spec. -* -* Other values are reserved for future versions. - */ -#define DMI_SBCS_SBVERSION_OFFSET 29 -#define DMI_SBCS_SBVERSION_LENGTH 3 -#define DMI_SBCS_SBVERSION (0x7U << DMI_SBCS_SBVERSION_OFFSET) -/* -* Set when the debugger attempts to read data while a read is in -* progress, or when the debugger initiates a new access while one is -* already in progress (while \Fsbbusy is set). It remains set until -* it's explicitly cleared by the debugger. -* -* While this field is set, no more system bus accesses can be -* initiated by the Debug Module. - */ -#define DMI_SBCS_SBBUSYERROR_OFFSET 22 -#define DMI_SBCS_SBBUSYERROR_LENGTH 1 -#define DMI_SBCS_SBBUSYERROR (0x1U << DMI_SBCS_SBBUSYERROR_OFFSET) -/* -* When 1, indicates the system bus master is busy. (Whether the -* system bus itself is busy is related, but not the same thing.) This -* bit goes high immediately when a read or write is requested for any -* reason, and does not go low until the access is fully completed. -* -* Writes to \Rsbcs while \Fsbbusy is high result in undefined -* behavior. A debugger must not write to \Rsbcs until it reads -* \Fsbbusy as 0. - */ -#define DMI_SBCS_SBBUSY_OFFSET 21 -#define DMI_SBCS_SBBUSY_LENGTH 1 -#define DMI_SBCS_SBBUSY (0x1U << DMI_SBCS_SBBUSY_OFFSET) -/* -* When 1, every write to \Rsbaddresszero automatically triggers a -* system bus read at the new address. - */ -#define DMI_SBCS_SBREADONADDR_OFFSET 20 -#define DMI_SBCS_SBREADONADDR_LENGTH 1 -#define DMI_SBCS_SBREADONADDR (0x1U << DMI_SBCS_SBREADONADDR_OFFSET) -/* -* Select the access size to use for system bus accesses. -* -* 0: 8-bit -* -* 1: 16-bit -* -* 2: 32-bit -* -* 3: 64-bit -* -* 4: 128-bit -* -* If \Fsbaccess has an unsupported value when the DM starts a bus -* access, the access is not performed and \Fsberror is set to 4. - */ -#define DMI_SBCS_SBACCESS_OFFSET 17 -#define DMI_SBCS_SBACCESS_LENGTH 3 -#define DMI_SBCS_SBACCESS (0x7U << DMI_SBCS_SBACCESS_OFFSET) -/* -* When 1, {\tt sbaddress} is incremented by the access size (in -* bytes) selected in \Fsbaccess after every system bus access. - */ -#define DMI_SBCS_SBAUTOINCREMENT_OFFSET 16 -#define DMI_SBCS_SBAUTOINCREMENT_LENGTH 1 -#define DMI_SBCS_SBAUTOINCREMENT (0x1U << DMI_SBCS_SBAUTOINCREMENT_OFFSET) -/* -* When 1, every read from \Rsbdatazero automatically triggers a -* system bus read at the (possibly auto-incremented) address. - */ -#define DMI_SBCS_SBREADONDATA_OFFSET 15 -#define DMI_SBCS_SBREADONDATA_LENGTH 1 -#define DMI_SBCS_SBREADONDATA (0x1U << DMI_SBCS_SBREADONDATA_OFFSET) -/* -* When the Debug Module's system bus -* master encounters an error, this field gets set. The bits in this -* field remain set until they are cleared by writing 1 to them. -* While this field is non-zero, no more system bus accesses can be -* initiated by the Debug Module. -* -* An implementation may report ``Other'' (7) for any error condition. -* -* 0: There was no bus error. -* -* 1: There was a timeout. -* -* 2: A bad address was accessed. -* -* 3: There was an alignment error. -* -* 4: An access of unsupported size was requested. -* -* 7: Other. - */ -#define DMI_SBCS_SBERROR_OFFSET 12 -#define DMI_SBCS_SBERROR_LENGTH 3 -#define DMI_SBCS_SBERROR (0x7U << DMI_SBCS_SBERROR_OFFSET) -/* -* Width of system bus addresses in bits. (0 indicates there is no bus -* access support.) - */ -#define DMI_SBCS_SBASIZE_OFFSET 5 -#define DMI_SBCS_SBASIZE_LENGTH 7 -#define DMI_SBCS_SBASIZE (0x7fU << DMI_SBCS_SBASIZE_OFFSET) -/* -* 1 when 128-bit system bus accesses are supported. - */ -#define DMI_SBCS_SBACCESS128_OFFSET 4 -#define DMI_SBCS_SBACCESS128_LENGTH 1 -#define DMI_SBCS_SBACCESS128 (0x1U << DMI_SBCS_SBACCESS128_OFFSET) -/* -* 1 when 64-bit system bus accesses are supported. - */ -#define DMI_SBCS_SBACCESS64_OFFSET 3 -#define DMI_SBCS_SBACCESS64_LENGTH 1 -#define DMI_SBCS_SBACCESS64 (0x1U << DMI_SBCS_SBACCESS64_OFFSET) -/* -* 1 when 32-bit system bus accesses are supported. - */ -#define DMI_SBCS_SBACCESS32_OFFSET 2 -#define DMI_SBCS_SBACCESS32_LENGTH 1 -#define DMI_SBCS_SBACCESS32 (0x1U << DMI_SBCS_SBACCESS32_OFFSET) -/* -* 1 when 16-bit system bus accesses are supported. - */ -#define DMI_SBCS_SBACCESS16_OFFSET 1 -#define DMI_SBCS_SBACCESS16_LENGTH 1 -#define DMI_SBCS_SBACCESS16 (0x1U << DMI_SBCS_SBACCESS16_OFFSET) -/* -* 1 when 8-bit system bus accesses are supported. - */ -#define DMI_SBCS_SBACCESS8_OFFSET 0 -#define DMI_SBCS_SBACCESS8_LENGTH 1 -#define DMI_SBCS_SBACCESS8 (0x1U << DMI_SBCS_SBACCESS8_OFFSET) -#define DMI_SBADDRESS0 0x39 -/* -* Accesses bits 31:0 of the physical address in {\tt sbaddress}. - */ -#define DMI_SBADDRESS0_ADDRESS_OFFSET 0 -#define DMI_SBADDRESS0_ADDRESS_LENGTH 32 -#define DMI_SBADDRESS0_ADDRESS (0xffffffffU << DMI_SBADDRESS0_ADDRESS_OFFSET) -#define DMI_SBADDRESS1 0x3a -/* -* Accesses bits 63:32 of the physical address in {\tt sbaddress} (if -* the system address bus is that wide). - */ -#define DMI_SBADDRESS1_ADDRESS_OFFSET 0 -#define DMI_SBADDRESS1_ADDRESS_LENGTH 32 -#define DMI_SBADDRESS1_ADDRESS (0xffffffffU << DMI_SBADDRESS1_ADDRESS_OFFSET) -#define DMI_SBADDRESS2 0x3b -/* -* Accesses bits 95:64 of the physical address in {\tt sbaddress} (if -* the system address bus is that wide). - */ -#define DMI_SBADDRESS2_ADDRESS_OFFSET 0 -#define DMI_SBADDRESS2_ADDRESS_LENGTH 32 -#define DMI_SBADDRESS2_ADDRESS (0xffffffffU << DMI_SBADDRESS2_ADDRESS_OFFSET) -#define DMI_SBADDRESS3 0x37 -/* -* Accesses bits 127:96 of the physical address in {\tt sbaddress} (if -* the system address bus is that wide). - */ -#define DMI_SBADDRESS3_ADDRESS_OFFSET 0 -#define DMI_SBADDRESS3_ADDRESS_LENGTH 32 -#define DMI_SBADDRESS3_ADDRESS (0xffffffffU << DMI_SBADDRESS3_ADDRESS_OFFSET) -#define DMI_SBDATA0 0x3c -/* -* Accesses bits 31:0 of {\tt sbdata}. - */ -#define DMI_SBDATA0_DATA_OFFSET 0 -#define DMI_SBDATA0_DATA_LENGTH 32 -#define DMI_SBDATA0_DATA (0xffffffffU << DMI_SBDATA0_DATA_OFFSET) -#define DMI_SBDATA1 0x3d -/* -* Accesses bits 63:32 of {\tt sbdata} (if the system bus is that -* wide). - */ -#define DMI_SBDATA1_DATA_OFFSET 0 -#define DMI_SBDATA1_DATA_LENGTH 32 -#define DMI_SBDATA1_DATA (0xffffffffU << DMI_SBDATA1_DATA_OFFSET) -#define DMI_SBDATA2 0x3e + * This field is 1 when all currently selected harts do not exist in + * this platform. + */ +#define DM_DMSTATUS_ALLNONEXISTENT_OFFSET 15 +#define DM_DMSTATUS_ALLNONEXISTENT_LENGTH 1 +#define DM_DMSTATUS_ALLNONEXISTENT (0x1U << DM_DMSTATUS_ALLNONEXISTENT_OFFSET) +/* + * This field is 1 when any currently selected hart does not exist in + * this platform. + */ +#define DM_DMSTATUS_ANYNONEXISTENT_OFFSET 14 +#define DM_DMSTATUS_ANYNONEXISTENT_LENGTH 1 +#define DM_DMSTATUS_ANYNONEXISTENT (0x1U << DM_DMSTATUS_ANYNONEXISTENT_OFFSET) +/* + * This field is 1 when all currently selected harts are unavailable. + */ +#define DM_DMSTATUS_ALLUNAVAIL_OFFSET 13 +#define DM_DMSTATUS_ALLUNAVAIL_LENGTH 1 +#define DM_DMSTATUS_ALLUNAVAIL (0x1U << DM_DMSTATUS_ALLUNAVAIL_OFFSET) +/* + * This field is 1 when any currently selected hart is unavailable. + */ +#define DM_DMSTATUS_ANYUNAVAIL_OFFSET 12 +#define DM_DMSTATUS_ANYUNAVAIL_LENGTH 1 +#define DM_DMSTATUS_ANYUNAVAIL (0x1U << DM_DMSTATUS_ANYUNAVAIL_OFFSET) +/* + * This field is 1 when all currently selected harts are running. + */ +#define DM_DMSTATUS_ALLRUNNING_OFFSET 11 +#define DM_DMSTATUS_ALLRUNNING_LENGTH 1 +#define DM_DMSTATUS_ALLRUNNING (0x1U << DM_DMSTATUS_ALLRUNNING_OFFSET) +/* + * This field is 1 when any currently selected hart is running. + */ +#define DM_DMSTATUS_ANYRUNNING_OFFSET 10 +#define DM_DMSTATUS_ANYRUNNING_LENGTH 1 +#define DM_DMSTATUS_ANYRUNNING (0x1U << DM_DMSTATUS_ANYRUNNING_OFFSET) +/* + * This field is 1 when all currently selected harts are halted. + */ +#define DM_DMSTATUS_ALLHALTED_OFFSET 9 +#define DM_DMSTATUS_ALLHALTED_LENGTH 1 +#define DM_DMSTATUS_ALLHALTED (0x1U << DM_DMSTATUS_ALLHALTED_OFFSET) +/* + * This field is 1 when any currently selected hart is halted. + */ +#define DM_DMSTATUS_ANYHALTED_OFFSET 8 +#define DM_DMSTATUS_ANYHALTED_LENGTH 1 +#define DM_DMSTATUS_ANYHALTED (0x1U << DM_DMSTATUS_ANYHALTED_OFFSET) +/* + * 0: Authentication is required before using the DM. + * + * 1: The authentication check has passed. + * + * On components that don't implement authentication, this bit must be + * preset as 1. + */ +#define DM_DMSTATUS_AUTHENTICATED_OFFSET 7 +#define DM_DMSTATUS_AUTHENTICATED_LENGTH 1 +#define DM_DMSTATUS_AUTHENTICATED (0x1U << DM_DMSTATUS_AUTHENTICATED_OFFSET) +/* + * 0: The authentication module is ready to process the next + * read/write to \RdmAuthdata. + * + * 1: The authentication module is busy. Accessing \RdmAuthdata results + * in unspecified behavior. + * + * \FdmDmstatusAuthbusy only becomes set in immediate response to an access to + * \RdmAuthdata. + */ +#define DM_DMSTATUS_AUTHBUSY_OFFSET 6 +#define DM_DMSTATUS_AUTHBUSY_LENGTH 1 +#define DM_DMSTATUS_AUTHBUSY (0x1U << DM_DMSTATUS_AUTHBUSY_OFFSET) +/* + * 1 if this Debug Module supports halt-on-reset functionality + * controllable by the \FdmDmcontrolSetresethaltreq and \FdmDmcontrolClrresethaltreq bits. + * 0 otherwise. + */ +#define DM_DMSTATUS_HASRESETHALTREQ_OFFSET 5 +#define DM_DMSTATUS_HASRESETHALTREQ_LENGTH 1 +#define DM_DMSTATUS_HASRESETHALTREQ (0x1U << DM_DMSTATUS_HASRESETHALTREQ_OFFSET) +/* + * 0: \RdmConfstrptrZero--\RdmConfstrptrThree hold information which + * is not relevant to the configuration string. + * + * 1: \RdmConfstrptrZero--\RdmConfstrptrThree hold the address of the + * configuration string. + */ +#define DM_DMSTATUS_CONFSTRPTRVALID_OFFSET 4 +#define DM_DMSTATUS_CONFSTRPTRVALID_LENGTH 1 +#define DM_DMSTATUS_CONFSTRPTRVALID (0x1U << DM_DMSTATUS_CONFSTRPTRVALID_OFFSET) +/* + * 0: There is no Debug Module present. + * + * 1: There is a Debug Module and it conforms to version 0.11 of this + * specification. + * + * 2: There is a Debug Module and it conforms to version 0.13 of this + * specification. + * + * 3: There is a Debug Module and it conforms to version 0.14 of this + * specification. + * + * 15: There is a Debug Module but it does not conform to any + * available version of this spec. + */ +#define DM_DMSTATUS_VERSION_OFFSET 0 +#define DM_DMSTATUS_VERSION_LENGTH 4 +#define DM_DMSTATUS_VERSION (0xfU << DM_DMSTATUS_VERSION_OFFSET) +#define DM_DMCONTROL 0x10 +/* + * Writing 0 clears the halt request bit for all currently selected + * harts. This may cancel outstanding halt requests for those harts. + * + * Writing 1 sets the halt request bit for all currently selected + * harts. Running harts will halt whenever their halt request bit is + * set. + * + * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. + */ +#define DM_DMCONTROL_HALTREQ_OFFSET 31 +#define DM_DMCONTROL_HALTREQ_LENGTH 1 +#define DM_DMCONTROL_HALTREQ (0x1U << DM_DMCONTROL_HALTREQ_OFFSET) +/* + * Writing 1 causes the currently selected harts to resume once, if + * they are halted when the write occurs. It also clears the resume + * ack bit for those harts. + * + * \FdmDmcontrolResumereq is ignored if \FdmDmcontrolHaltreq is set. + * + * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. + */ +#define DM_DMCONTROL_RESUMEREQ_OFFSET 30 +#define DM_DMCONTROL_RESUMEREQ_LENGTH 1 +#define DM_DMCONTROL_RESUMEREQ (0x1U << DM_DMCONTROL_RESUMEREQ_OFFSET) +/* + * This optional field writes the reset bit for all the currently + * selected harts. To perform a reset the debugger writes 1, and then + * writes 0 to deassert the reset signal. + * + * While this bit is 1, the debugger must not change which harts are + * selected. + * + * If this feature is not implemented, the bit always stays 0, so + * after writing 1 the debugger can read the register back to see if + * the feature is supported. + * + * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. + */ +#define DM_DMCONTROL_HARTRESET_OFFSET 29 +#define DM_DMCONTROL_HARTRESET_LENGTH 1 +#define DM_DMCONTROL_HARTRESET (0x1U << DM_DMCONTROL_HARTRESET_OFFSET) +/* + * 0: No effect. + * + * 1: Clears {\tt havereset} for any selected harts. + * + * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. + */ +#define DM_DMCONTROL_ACKHAVERESET_OFFSET 28 +#define DM_DMCONTROL_ACKHAVERESET_LENGTH 1 +#define DM_DMCONTROL_ACKHAVERESET (0x1U << DM_DMCONTROL_ACKHAVERESET_OFFSET) +/* + * Selects the definition of currently selected harts. + * + * 0: There is a single currently selected hart, that is selected by \Fhartsel. + * + * 1: There may be multiple currently selected harts -- the hart + * selected by \Fhartsel, plus those selected by the hart array mask + * register. + * + * An implementation which does not implement the hart array mask register + * must tie this field to 0. A debugger which wishes to use the hart array + * mask register feature should set this bit and read back to see if the functionality + * is supported. + */ +#define DM_DMCONTROL_HASEL_OFFSET 26 +#define DM_DMCONTROL_HASEL_LENGTH 1 +#define DM_DMCONTROL_HASEL (0x1U << DM_DMCONTROL_HASEL_OFFSET) +/* + * The low 10 bits of \Fhartsel: the DM-specific index of the hart to + * select. This hart is always part of the currently selected harts. + */ +#define DM_DMCONTROL_HARTSELLO_OFFSET 16 +#define DM_DMCONTROL_HARTSELLO_LENGTH 10 +#define DM_DMCONTROL_HARTSELLO (0x3ffU << DM_DMCONTROL_HARTSELLO_OFFSET) +/* + * The high 10 bits of \Fhartsel: the DM-specific index of the hart to + * select. This hart is always part of the currently selected harts. + */ +#define DM_DMCONTROL_HARTSELHI_OFFSET 6 +#define DM_DMCONTROL_HARTSELHI_LENGTH 10 +#define DM_DMCONTROL_HARTSELHI (0x3ffU << DM_DMCONTROL_HARTSELHI_OFFSET) +/* + * This optional field writes the halt-on-reset request bit for all + * currently selected harts, unless \FdmDmcontrolClrresethaltreq is + * simultaneously set to 1. + * When set to 1, each selected hart will halt upon the next deassertion + * of its reset. The halt-on-reset request bit is not automatically + * cleared. The debugger must write to \FdmDmcontrolClrresethaltreq to clear it. + * + * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. + * + * If \FdmDmstatusHasresethaltreq is 0, this field is not implemented. + */ +#define DM_DMCONTROL_SETRESETHALTREQ_OFFSET 3 +#define DM_DMCONTROL_SETRESETHALTREQ_LENGTH 1 +#define DM_DMCONTROL_SETRESETHALTREQ (0x1U << DM_DMCONTROL_SETRESETHALTREQ_OFFSET) +/* + * This optional field clears the halt-on-reset request bit for all + * currently selected harts. + * + * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel. + */ +#define DM_DMCONTROL_CLRRESETHALTREQ_OFFSET 2 +#define DM_DMCONTROL_CLRRESETHALTREQ_LENGTH 1 +#define DM_DMCONTROL_CLRRESETHALTREQ (0x1U << DM_DMCONTROL_CLRRESETHALTREQ_OFFSET) +/* + * This bit controls the reset signal from the DM to the rest of the + * system. The signal should reset every part of the system, including + * every hart, except for the DM and any logic required to access the + * DM. + * To perform a system reset the debugger writes 1, + * and then writes 0 + * to deassert the reset. + */ +#define DM_DMCONTROL_NDMRESET_OFFSET 1 +#define DM_DMCONTROL_NDMRESET_LENGTH 1 +#define DM_DMCONTROL_NDMRESET (0x1U << DM_DMCONTROL_NDMRESET_OFFSET) +/* + * This bit serves as a reset signal for the Debug Module itself. + * + * 0: The module's state, including authentication mechanism, + * takes its reset values (the \FdmDmcontrolDmactive bit is the only bit which can + * be written to something other than its reset value). Any accesses + * to the module may fail. Specifically, \FdmDmstatusVersion may not return + * correct data. + * + * 1: The module functions normally. After writing 1, the debugger should + * poll \RdmDmcontrol until \FdmDmcontrolDmactive is high. Hardware may + * take an arbitrarily long time to initialize and will indicate completion + * by setting dmactive to 1. + * + * No other mechanism should exist that may result in resetting the + * Debug Module after power up. + * + * A debugger may pulse this bit low to get the Debug Module into a + * known state. + * + * Implementations may pay attention to this bit to further aid + * debugging, for example by preventing the Debug Module from being + * power gated while debugging is active. + */ +#define DM_DMCONTROL_DMACTIVE_OFFSET 0 +#define DM_DMCONTROL_DMACTIVE_LENGTH 1 +#define DM_DMCONTROL_DMACTIVE (0x1U << DM_DMCONTROL_DMACTIVE_OFFSET) +#define DM_HARTINFO 0x12 +/* + * Number of {\tt dscratch} registers available for the debugger + * to use during program buffer execution, starting from \RcsrDscratchZero. + * The debugger can make no assumptions about the contents of these + * registers between commands. + */ +#define DM_HARTINFO_NSCRATCH_OFFSET 20 +#define DM_HARTINFO_NSCRATCH_LENGTH 4 +#define DM_HARTINFO_NSCRATCH (0xfU << DM_HARTINFO_NSCRATCH_OFFSET) +/* + * 0: The {\tt data} registers are shadowed in the hart by CSRs. + * Each CSR is DXLEN bits in size, and corresponds + * to a single argument, per Table~\ref{tab:datareg}. + * + * 1: The {\tt data} registers are shadowed in the hart's memory map. + * Each register takes up 4 bytes in the memory map. + */ +#define DM_HARTINFO_DATAACCESS_OFFSET 16 +#define DM_HARTINFO_DATAACCESS_LENGTH 1 +#define DM_HARTINFO_DATAACCESS (0x1U << DM_HARTINFO_DATAACCESS_OFFSET) +/* + * If \FdmHartinfoDataaccess is 0: Number of CSRs dedicated to + * shadowing the {\tt data} registers. + * + * If \FdmHartinfoDataaccess is 1: Number of 32-bit words in the memory map + * dedicated to shadowing the {\tt data} registers. + * + * Since there are at most 12 {\tt data} registers, the value in this + * register must be 12 or smaller. + */ +#define DM_HARTINFO_DATASIZE_OFFSET 12 +#define DM_HARTINFO_DATASIZE_LENGTH 4 +#define DM_HARTINFO_DATASIZE (0xfU << DM_HARTINFO_DATASIZE_OFFSET) +/* + * If \FdmHartinfoDataaccess is 0: The number of the first CSR dedicated to + * shadowing the {\tt data} registers. + * + * If \FdmHartinfoDataaccess is 1: Address of RAM where the data + * registers are shadowed. This address is sign extended giving a + * range of -2048 to 2047, easily addressed with a load or store using + * \Xzero as the address register. + */ +#define DM_HARTINFO_DATAADDR_OFFSET 0 +#define DM_HARTINFO_DATAADDR_LENGTH 12 +#define DM_HARTINFO_DATAADDR (0xfffU << DM_HARTINFO_DATAADDR_OFFSET) +#define DM_HAWINDOWSEL 0x14 +/* + * The high bits of this field may be tied to 0, depending on how large + * the array mask register is. E.g.\ on a system with 48 harts only bit 0 + * of this field may actually be writable. + */ +#define DM_HAWINDOWSEL_HAWINDOWSEL_OFFSET 0 +#define DM_HAWINDOWSEL_HAWINDOWSEL_LENGTH 15 +#define DM_HAWINDOWSEL_HAWINDOWSEL (0x7fffU << DM_HAWINDOWSEL_HAWINDOWSEL_OFFSET) +#define DM_HAWINDOW 0x15 +#define DM_HAWINDOW_MASKDATA_OFFSET 0 +#define DM_HAWINDOW_MASKDATA_LENGTH 32 +#define DM_HAWINDOW_MASKDATA (0xffffffffU << DM_HAWINDOW_MASKDATA_OFFSET) +#define DM_ABSTRACTCS 0x16 +/* + * Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 16. + */ +#define DM_ABSTRACTCS_PROGBUFSIZE_OFFSET 24 +#define DM_ABSTRACTCS_PROGBUFSIZE_LENGTH 5 +#define DM_ABSTRACTCS_PROGBUFSIZE (0x1fU << DM_ABSTRACTCS_PROGBUFSIZE_OFFSET) +/* + * 1: An abstract command is currently being executed. + * + * This bit is set as soon as \RdmCommand is written, and is + * not cleared until that command has completed. + */ +#define DM_ABSTRACTCS_BUSY_OFFSET 12 +#define DM_ABSTRACTCS_BUSY_LENGTH 1 +#define DM_ABSTRACTCS_BUSY (0x1U << DM_ABSTRACTCS_BUSY_OFFSET) +/* + * This optional bit controls whether program buffer and abstract + * memory accesses are performed with the exact and full set of + * permission checks that apply based on the current architectural + * state of the hart performing the access, or with a relaxed set of + * permission checks (e.g. PMP restrictions are ignored). The + * details of the latter are implementation-specific. When set to 0, + * full permissions apply; when set to 1, relaxed permissions apply. + */ +#define DM_ABSTRACTCS_RELAXEDPRIV_OFFSET 11 +#define DM_ABSTRACTCS_RELAXEDPRIV_LENGTH 1 +#define DM_ABSTRACTCS_RELAXEDPRIV (0x1U << DM_ABSTRACTCS_RELAXEDPRIV_OFFSET) +/* + * Gets set if an abstract command fails. The bits in this field remain set until + * they are cleared by writing 1 to them. No abstract command is + * started until the value is reset to 0. + * + * This field only contains a valid value if \FdmAbstractcsBusy is 0. + * + * 0 (none): No error. + * + * 1 (busy): An abstract command was executing while \RdmCommand, + * \RdmAbstractcs, or \RdmAbstractauto was written, or when one + * of the {\tt data} or {\tt progbuf} registers was read or written. + * This status is only written if \FdmAbstractcsCmderr contains 0. + * + * 2 (not supported): The command in \RdmCommand is not supported. It + * may be supported with different options set, but it will not be + * supported at a later time when the hart or system state are + * different. + * + * 3 (exception): An exception occurred while executing the command + * (e.g.\ while executing the Program Buffer). + * + * 4 (halt/resume): The abstract command couldn't execute because the + * hart wasn't in the required state (running/halted), or unavailable. + * + * 5 (bus): The abstract command failed due to a bus error (e.g.\ + * alignment, access size, or timeout). + * + * 6: Reserved for future use. + * + * 7 (other): The command failed for another reason. + */ +#define DM_ABSTRACTCS_CMDERR_OFFSET 8 +#define DM_ABSTRACTCS_CMDERR_LENGTH 3 +#define DM_ABSTRACTCS_CMDERR (0x7U << DM_ABSTRACTCS_CMDERR_OFFSET) +/* + * Number of {\tt data} registers that are implemented as part of the + * abstract command interface. Valid sizes are 1 -- 12. + */ +#define DM_ABSTRACTCS_DATACOUNT_OFFSET 0 +#define DM_ABSTRACTCS_DATACOUNT_LENGTH 4 +#define DM_ABSTRACTCS_DATACOUNT (0xfU << DM_ABSTRACTCS_DATACOUNT_OFFSET) +#define DM_COMMAND 0x17 +/* + * The type determines the overall functionality of this + * abstract command. + */ +#define DM_COMMAND_CMDTYPE_OFFSET 24 +#define DM_COMMAND_CMDTYPE_LENGTH 8 +#define DM_COMMAND_CMDTYPE (0xffU << DM_COMMAND_CMDTYPE_OFFSET) +/* + * This field is interpreted in a command-specific manner, + * described for each abstract command. + */ +#define DM_COMMAND_CONTROL_OFFSET 0 +#define DM_COMMAND_CONTROL_LENGTH 24 +#define DM_COMMAND_CONTROL (0xffffffU << DM_COMMAND_CONTROL_OFFSET) +#define DM_ABSTRACTAUTO 0x18 +/* + * When a bit in this field is 1, read or write accesses to the + * corresponding {\tt progbuf} word cause the command in \RdmCommand to + * be executed again. + */ +#define DM_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET 16 +#define DM_ABSTRACTAUTO_AUTOEXECPROGBUF_LENGTH 16 +#define DM_ABSTRACTAUTO_AUTOEXECPROGBUF (0xffffU << DM_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET) +/* + * When a bit in this field is 1, read or write accesses to the + * corresponding {\tt data} word cause the command in \RdmCommand to be + * executed again. + */ +#define DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET 0 +#define DM_ABSTRACTAUTO_AUTOEXECDATA_LENGTH 12 +#define DM_ABSTRACTAUTO_AUTOEXECDATA (0xfffU << DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET) +#define DM_CONFSTRPTR0 0x19 +#define DM_CONFSTRPTR0_ADDR_OFFSET 0 +#define DM_CONFSTRPTR0_ADDR_LENGTH 32 +#define DM_CONFSTRPTR0_ADDR (0xffffffffU << DM_CONFSTRPTR0_ADDR_OFFSET) +#define DM_CONFSTRPTR1 0x1a +#define DM_CONFSTRPTR1_ADDR_OFFSET 0 +#define DM_CONFSTRPTR1_ADDR_LENGTH 32 +#define DM_CONFSTRPTR1_ADDR (0xffffffffU << DM_CONFSTRPTR1_ADDR_OFFSET) +#define DM_CONFSTRPTR2 0x1b +#define DM_CONFSTRPTR2_ADDR_OFFSET 0 +#define DM_CONFSTRPTR2_ADDR_LENGTH 32 +#define DM_CONFSTRPTR2_ADDR (0xffffffffU << DM_CONFSTRPTR2_ADDR_OFFSET) +#define DM_CONFSTRPTR3 0x1c +#define DM_CONFSTRPTR3_ADDR_OFFSET 0 +#define DM_CONFSTRPTR3_ADDR_LENGTH 32 +#define DM_CONFSTRPTR3_ADDR (0xffffffffU << DM_CONFSTRPTR3_ADDR_OFFSET) +#define DM_NEXTDM 0x1d +#define DM_NEXTDM_ADDR_OFFSET 0 +#define DM_NEXTDM_ADDR_LENGTH 32 +#define DM_NEXTDM_ADDR (0xffffffffU << DM_NEXTDM_ADDR_OFFSET) +#define DM_DATA0 0x04 +#define DM_DATA0_DATA_OFFSET 0 +#define DM_DATA0_DATA_LENGTH 32 +#define DM_DATA0_DATA (0xffffffffU << DM_DATA0_DATA_OFFSET) +#define DM_DATA11 0x0f +#define DM_PROGBUF0 0x20 +#define DM_PROGBUF0_DATA_OFFSET 0 +#define DM_PROGBUF0_DATA_LENGTH 32 +#define DM_PROGBUF0_DATA (0xffffffffU << DM_PROGBUF0_DATA_OFFSET) +#define DM_PROGBUF15 0x2f +#define DM_AUTHDATA 0x30 +#define DM_AUTHDATA_DATA_OFFSET 0 +#define DM_AUTHDATA_DATA_LENGTH 32 +#define DM_AUTHDATA_DATA (0xffffffffU << DM_AUTHDATA_DATA_OFFSET) +#define DM_DMCS2 0x32 +/* + * 0: The remaining fields in this register configure halt groups. + * + * 1: The remaining fields in this register configure resume groups. + */ +#define DM_DMCS2_GROUPTYPE_OFFSET 11 +#define DM_DMCS2_GROUPTYPE_LENGTH 1 +#define DM_DMCS2_GROUPTYPE (0x1U << DM_DMCS2_GROUPTYPE_OFFSET) +/* + * This field contains the currently selected external trigger. + * + * If a non-existent trigger value is written here, the hardware will + * change it to a valid one or 0 if no external triggers exist. + */ +#define DM_DMCS2_EXTTRIGGER_OFFSET 7 +#define DM_DMCS2_EXTTRIGGER_LENGTH 4 +#define DM_DMCS2_EXTTRIGGER (0xfU << DM_DMCS2_EXTTRIGGER_OFFSET) +/* + * When \FdmDmcsTwoHgselect is 0, contains the group of the hart + * specified by \Fhartsel. + * + * When \FdmDmcsTwoHgselect is 1, contains the group of the external + * trigger selected by \FdmDmcsTwoExttrigger. + * + * Writes only have an effect if \FdmDmcsTwoHgwrite is also written 1. + * + * Group numbers are contiguous starting at 0, with the highest number + * being implementation-dependent, and possibly different between + * different group types. Debuggers should read back this field after + * writing to confirm they are using a hart group that is supported. + * + * If groups aren't implemented, then this entire field is 0. + */ +#define DM_DMCS2_GROUP_OFFSET 2 +#define DM_DMCS2_GROUP_LENGTH 5 +#define DM_DMCS2_GROUP (0x1fU << DM_DMCS2_GROUP_OFFSET) +/* + * When \FdmDmcsTwoHgselect is 0, writing 1 changes the group of all + * selected harts to the value written to \FdmDmcsTwoGroup. + * + * When 1 is written and \FdmDmcsTwoHgselect is 0, for every selected + * hart the DM will change its group to the value written to \FdmDmcsTwoGroup, + * if the hardware supports that group for that hart. + * + * When 1 is written and \FdmDmcsTwoHgselect is 1, the DM will change + * the group of the external trigger selected by \FdmDmcsTwoExttrigger + * to the value written to \FdmDmcsTwoGroup, if the hardware supports + * that group for that trigger. + * + * Writing 0 has no effect. + */ +#define DM_DMCS2_HGWRITE_OFFSET 1 +#define DM_DMCS2_HGWRITE_LENGTH 1 +#define DM_DMCS2_HGWRITE (0x1U << DM_DMCS2_HGWRITE_OFFSET) +/* + * 0: Operate on harts. + * + * 1: Operate on external triggers. + * + * If there are no external triggers, this field must be tied to 0. + */ +#define DM_DMCS2_HGSELECT_OFFSET 0 +#define DM_DMCS2_HGSELECT_LENGTH 1 +#define DM_DMCS2_HGSELECT (0x1U << DM_DMCS2_HGSELECT_OFFSET) +#define DM_HALTSUM0 0x40 +#define DM_HALTSUM0_HALTSUM0_OFFSET 0 +#define DM_HALTSUM0_HALTSUM0_LENGTH 32 +#define DM_HALTSUM0_HALTSUM0 (0xffffffffU << DM_HALTSUM0_HALTSUM0_OFFSET) +#define DM_HALTSUM1 0x13 +#define DM_HALTSUM1_HALTSUM1_OFFSET 0 +#define DM_HALTSUM1_HALTSUM1_LENGTH 32 +#define DM_HALTSUM1_HALTSUM1 (0xffffffffU << DM_HALTSUM1_HALTSUM1_OFFSET) +#define DM_HALTSUM2 0x34 +#define DM_HALTSUM2_HALTSUM2_OFFSET 0 +#define DM_HALTSUM2_HALTSUM2_LENGTH 32 +#define DM_HALTSUM2_HALTSUM2 (0xffffffffU << DM_HALTSUM2_HALTSUM2_OFFSET) +#define DM_HALTSUM3 0x35 +#define DM_HALTSUM3_HALTSUM3_OFFSET 0 +#define DM_HALTSUM3_HALTSUM3_LENGTH 32 +#define DM_HALTSUM3_HALTSUM3 (0xffffffffU << DM_HALTSUM3_HALTSUM3_OFFSET) +#define DM_SBCS 0x38 +/* + * 0: The System Bus interface conforms to mainline drafts of this + * spec older than 1 January, 2018. + * + * 1: The System Bus interface conforms to this version of the spec. + * + * Other values are reserved for future versions. + */ +#define DM_SBCS_SBVERSION_OFFSET 29 +#define DM_SBCS_SBVERSION_LENGTH 3 +#define DM_SBCS_SBVERSION (0x7U << DM_SBCS_SBVERSION_OFFSET) +/* + * Set when the debugger attempts to read data while a read is in + * progress, or when the debugger initiates a new access while one is + * already in progress (while \FdmSbcsSbbusy is set). It remains set until + * it's explicitly cleared by the debugger. + * + * While this field is set, no more system bus accesses can be + * initiated by the Debug Module. + */ +#define DM_SBCS_SBBUSYERROR_OFFSET 22 +#define DM_SBCS_SBBUSYERROR_LENGTH 1 +#define DM_SBCS_SBBUSYERROR (0x1U << DM_SBCS_SBBUSYERROR_OFFSET) +/* + * When 1, indicates the system bus master is busy. (Whether the + * system bus itself is busy is related, but not the same thing.) This + * bit goes high immediately when a read or write is requested for any + * reason, and does not go low until the access is fully completed. + * + * Writes to \RdmSbcs while \FdmSbcsSbbusy is high result in undefined + * behavior. A debugger must not write to \RdmSbcs until it reads + * \FdmSbcsSbbusy as 0. + */ +#define DM_SBCS_SBBUSY_OFFSET 21 +#define DM_SBCS_SBBUSY_LENGTH 1 +#define DM_SBCS_SBBUSY (0x1U << DM_SBCS_SBBUSY_OFFSET) +/* + * When 1, every write to \RdmSbaddressZero automatically triggers a + * system bus read at the new address. + */ +#define DM_SBCS_SBREADONADDR_OFFSET 20 +#define DM_SBCS_SBREADONADDR_LENGTH 1 +#define DM_SBCS_SBREADONADDR (0x1U << DM_SBCS_SBREADONADDR_OFFSET) +/* + * Select the access size to use for system bus accesses. + * + * 0: 8-bit + * + * 1: 16-bit + * + * 2: 32-bit + * + * 3: 64-bit + * + * 4: 128-bit + * + * If \FdmSbcsSbaccess has an unsupported value when the DM starts a bus + * access, the access is not performed and \FdmSbcsSberror is set to 4. + */ +#define DM_SBCS_SBACCESS_OFFSET 17 +#define DM_SBCS_SBACCESS_LENGTH 3 +#define DM_SBCS_SBACCESS (0x7U << DM_SBCS_SBACCESS_OFFSET) +/* + * When 1, {\tt sbaddress} is incremented by the access size (in + * bytes) selected in \FdmSbcsSbaccess after every system bus access. + */ +#define DM_SBCS_SBAUTOINCREMENT_OFFSET 16 +#define DM_SBCS_SBAUTOINCREMENT_LENGTH 1 +#define DM_SBCS_SBAUTOINCREMENT (0x1U << DM_SBCS_SBAUTOINCREMENT_OFFSET) +/* + * When 1, every read from \RdmSbdataZero automatically triggers a + * system bus read at the (possibly auto-incremented) address. + */ +#define DM_SBCS_SBREADONDATA_OFFSET 15 +#define DM_SBCS_SBREADONDATA_LENGTH 1 +#define DM_SBCS_SBREADONDATA (0x1U << DM_SBCS_SBREADONDATA_OFFSET) +/* + * When the Debug Module's system bus + * master encounters an error, this field gets set. The bits in this + * field remain set until they are cleared by writing 1 to them. + * While this field is non-zero, no more system bus accesses can be + * initiated by the Debug Module. + * + * An implementation may report ``Other'' (7) for any error condition. + * + * 0: There was no bus error. + * + * 1: There was a timeout. + * + * 2: A bad address was accessed. + * + * 3: There was an alignment error. + * + * 4: An access of unsupported size was requested. + * + * 7: Other. + */ +#define DM_SBCS_SBERROR_OFFSET 12 +#define DM_SBCS_SBERROR_LENGTH 3 +#define DM_SBCS_SBERROR (0x7U << DM_SBCS_SBERROR_OFFSET) +/* + * Width of system bus addresses in bits. (0 indicates there is no bus + * access support.) + */ +#define DM_SBCS_SBASIZE_OFFSET 5 +#define DM_SBCS_SBASIZE_LENGTH 7 +#define DM_SBCS_SBASIZE (0x7fU << DM_SBCS_SBASIZE_OFFSET) +/* + * 1 when 128-bit system bus accesses are supported. + */ +#define DM_SBCS_SBACCESS128_OFFSET 4 +#define DM_SBCS_SBACCESS128_LENGTH 1 +#define DM_SBCS_SBACCESS128 (0x1U << DM_SBCS_SBACCESS128_OFFSET) +/* + * 1 when 64-bit system bus accesses are supported. + */ +#define DM_SBCS_SBACCESS64_OFFSET 3 +#define DM_SBCS_SBACCESS64_LENGTH 1 +#define DM_SBCS_SBACCESS64 (0x1U << DM_SBCS_SBACCESS64_OFFSET) +/* + * 1 when 32-bit system bus accesses are supported. + */ +#define DM_SBCS_SBACCESS32_OFFSET 2 +#define DM_SBCS_SBACCESS32_LENGTH 1 +#define DM_SBCS_SBACCESS32 (0x1U << DM_SBCS_SBACCESS32_OFFSET) +/* + * 1 when 16-bit system bus accesses are supported. + */ +#define DM_SBCS_SBACCESS16_OFFSET 1 +#define DM_SBCS_SBACCESS16_LENGTH 1 +#define DM_SBCS_SBACCESS16 (0x1U << DM_SBCS_SBACCESS16_OFFSET) +/* + * 1 when 8-bit system bus accesses are supported. + */ +#define DM_SBCS_SBACCESS8_OFFSET 0 +#define DM_SBCS_SBACCESS8_LENGTH 1 +#define DM_SBCS_SBACCESS8 (0x1U << DM_SBCS_SBACCESS8_OFFSET) +#define DM_SBADDRESS0 0x39 +/* + * Accesses bits 31:0 of the physical address in {\tt sbaddress}. + */ +#define DM_SBADDRESS0_ADDRESS_OFFSET 0 +#define DM_SBADDRESS0_ADDRESS_LENGTH 32 +#define DM_SBADDRESS0_ADDRESS (0xffffffffU << DM_SBADDRESS0_ADDRESS_OFFSET) +#define DM_SBADDRESS1 0x3a +/* + * Accesses bits 63:32 of the physical address in {\tt sbaddress} (if + * the system address bus is that wide). + */ +#define DM_SBADDRESS1_ADDRESS_OFFSET 0 +#define DM_SBADDRESS1_ADDRESS_LENGTH 32 +#define DM_SBADDRESS1_ADDRESS (0xffffffffU << DM_SBADDRESS1_ADDRESS_OFFSET) +#define DM_SBADDRESS2 0x3b +/* + * Accesses bits 95:64 of the physical address in {\tt sbaddress} (if + * the system address bus is that wide). + */ +#define DM_SBADDRESS2_ADDRESS_OFFSET 0 +#define DM_SBADDRESS2_ADDRESS_LENGTH 32 +#define DM_SBADDRESS2_ADDRESS (0xffffffffU << DM_SBADDRESS2_ADDRESS_OFFSET) +#define DM_SBADDRESS3 0x37 +/* + * Accesses bits 127:96 of the physical address in {\tt sbaddress} (if + * the system address bus is that wide). + */ +#define DM_SBADDRESS3_ADDRESS_OFFSET 0 +#define DM_SBADDRESS3_ADDRESS_LENGTH 32 +#define DM_SBADDRESS3_ADDRESS (0xffffffffU << DM_SBADDRESS3_ADDRESS_OFFSET) +#define DM_SBDATA0 0x3c +/* + * Accesses bits 31:0 of {\tt sbdata}. + */ +#define DM_SBDATA0_DATA_OFFSET 0 +#define DM_SBDATA0_DATA_LENGTH 32 +#define DM_SBDATA0_DATA (0xffffffffU << DM_SBDATA0_DATA_OFFSET) +#define DM_SBDATA1 0x3d +/* + * Accesses bits 63:32 of {\tt sbdata} (if the system bus is that + * wide). + */ +#define DM_SBDATA1_DATA_OFFSET 0 +#define DM_SBDATA1_DATA_LENGTH 32 +#define DM_SBDATA1_DATA (0xffffffffU << DM_SBDATA1_DATA_OFFSET) +#define DM_SBDATA2 0x3e /* -* Accesses bits 95:64 of {\tt sbdata} (if the system bus is that -* wide). + * Accesses bits 95:64 of {\tt sbdata} (if the system bus is that + * wide). */ -#define DMI_SBDATA2_DATA_OFFSET 0 -#define DMI_SBDATA2_DATA_LENGTH 32 -#define DMI_SBDATA2_DATA (0xffffffffU << DMI_SBDATA2_DATA_OFFSET) -#define DMI_SBDATA3 0x3f +#define DM_SBDATA2_DATA_OFFSET 0 +#define DM_SBDATA2_DATA_LENGTH 32 +#define DM_SBDATA2_DATA (0xffffffffU << DM_SBDATA2_DATA_OFFSET) +#define DM_SBDATA3 0x3f /* -* Accesses bits 127:96 of {\tt sbdata} (if the system bus is that -* wide). + * Accesses bits 127:96 of {\tt sbdata} (if the system bus is that + * wide). */ -#define DMI_SBDATA3_DATA_OFFSET 0 -#define DMI_SBDATA3_DATA_LENGTH 32 -#define DMI_SBDATA3_DATA (0xffffffffU << DMI_SBDATA3_DATA_OFFSET) -#define DMI_CUSTOM 0x1f -#define DMI_CUSTOM0 0x70 -#define DMI_CUSTOM15 0x7f +#define DM_SBDATA3_DATA_OFFSET 0 +#define DM_SBDATA3_DATA_LENGTH 32 +#define DM_SBDATA3_DATA (0xffffffffU << DM_SBDATA3_DATA_OFFSET) +#define DM_CUSTOM 0x1f +#define DM_CUSTOM0 0x70 +#define DM_CUSTOM15 0x7f #define SHORTNAME 0x123 /* -* Description of what this field is used for. + * Description of what this field is used for. */ #define SHORTNAME_FIELD_OFFSET 0 #define SHORTNAME_FIELD_LENGTH 8 #define SHORTNAME_FIELD (0xffU << SHORTNAME_FIELD_OFFSET) -#define AC_ACCESS_REGISTER None /* -* This is 0 to indicate Access Register Command. + * This is 0 to indicate Access Register Command. */ #define AC_ACCESS_REGISTER_CMDTYPE_OFFSET 24 #define AC_ACCESS_REGISTER_CMDTYPE_LENGTH 8 #define AC_ACCESS_REGISTER_CMDTYPE (0xffU << AC_ACCESS_REGISTER_CMDTYPE_OFFSET) /* -* 2: Access the lowest 32 bits of the register. -* -* 3: Access the lowest 64 bits of the register. -* -* 4: Access the lowest 128 bits of the register. -* -* If \Faarsize specifies a size larger than the register's actual size, -* then the access must fail. If a register is accessible, then reads of \Faarsize -* less than or equal to the register's actual size must be supported. -* -* This field controls the Argument Width as referenced in -* Table~\ref{tab:datareg}. + * 2: Access the lowest 32 bits of the register. + * + * 3: Access the lowest 64 bits of the register. + * + * 4: Access the lowest 128 bits of the register. + * + * If \FacAccessregisterAarsize specifies a size larger than the register's actual size, + * then the access must fail. If a register is accessible, then reads of \FacAccessregisterAarsize + * less than or equal to the register's actual size must be supported. + * + * This field controls the Argument Width as referenced in + * Table~\ref{tab:datareg}. */ #define AC_ACCESS_REGISTER_AARSIZE_OFFSET 20 #define AC_ACCESS_REGISTER_AARSIZE_LENGTH 3 #define AC_ACCESS_REGISTER_AARSIZE (0x7U << AC_ACCESS_REGISTER_AARSIZE_OFFSET) /* -* 0: No effect. This variant must be supported. -* -* 1: After a successful register access, \Fregno is incremented -* (wrapping around to 0). Supporting this variant is optional. + * 0: No effect. This variant must be supported. + * + * 1: After a successful register access, \FacAccessregisterRegno is + * incremented (wrapping around to 0). Supporting this variant is + * optional. It is undefined whether the increment happens when + * \FacAccessregisterTransfer is 0. */ #define AC_ACCESS_REGISTER_AARPOSTINCREMENT_OFFSET 19 #define AC_ACCESS_REGISTER_AARPOSTINCREMENT_LENGTH 1 #define AC_ACCESS_REGISTER_AARPOSTINCREMENT (0x1U << AC_ACCESS_REGISTER_AARPOSTINCREMENT_OFFSET) /* -* 0: No effect. This variant must be supported, and is the only -* supported one if \Fprogbufsize is 0. -* -* 1: Execute the program in the Program Buffer exactly once after -* performing the transfer, if any. Supporting this variant is -* optional. + * 0: No effect. This variant must be supported, and is the only + * supported one if \FdmAbstractcsProgbufsize is 0. + * + * 1: Execute the program in the Program Buffer exactly once after + * performing the transfer, if any. Supporting this variant is + * optional. */ #define AC_ACCESS_REGISTER_POSTEXEC_OFFSET 18 #define AC_ACCESS_REGISTER_POSTEXEC_LENGTH 1 #define AC_ACCESS_REGISTER_POSTEXEC (0x1U << AC_ACCESS_REGISTER_POSTEXEC_OFFSET) /* -* 0: Don't do the operation specified by \Fwrite. -* -* 1: Do the operation specified by \Fwrite. -* -* This bit can be used to just execute the Program Buffer without -* having to worry about placing valid values into \Faarsize or \Fregno. + * 0: Don't do the operation specified by \FacAccessregisterWrite. + * + * 1: Do the operation specified by \FacAccessregisterWrite. + * + * This bit can be used to just execute the Program Buffer without + * having to worry about placing valid values into \FacAccessregisterAarsize or \FacAccessregisterRegno. */ #define AC_ACCESS_REGISTER_TRANSFER_OFFSET 17 #define AC_ACCESS_REGISTER_TRANSFER_LENGTH 1 #define AC_ACCESS_REGISTER_TRANSFER (0x1U << AC_ACCESS_REGISTER_TRANSFER_OFFSET) /* -* When \Ftransfer is set: -* 0: Copy data from the specified register into {\tt arg0} portion -* of {\tt data}. -* -* 1: Copy data from {\tt arg0} portion of {\tt data} into the -* specified register. + * When \FacAccessregisterTransfer is set: + * 0: Copy data from the specified register into {\tt arg0} portion + * of {\tt data}. + * + * 1: Copy data from {\tt arg0} portion of {\tt data} into the + * specified register. */ #define AC_ACCESS_REGISTER_WRITE_OFFSET 16 #define AC_ACCESS_REGISTER_WRITE_LENGTH 1 #define AC_ACCESS_REGISTER_WRITE (0x1U << AC_ACCESS_REGISTER_WRITE_OFFSET) /* -* Number of the register to access, as described in -* Table~\ref{tab:regno}. -* \Rdpc may be used as an alias for PC if this command is -* supported on a non-halted hart. + * Number of the register to access, as described in + * Table~\ref{tab:regno}. + * \RcsrDpc may be used as an alias for PC if this command is + * supported on a non-halted hart. */ #define AC_ACCESS_REGISTER_REGNO_OFFSET 0 #define AC_ACCESS_REGISTER_REGNO_LENGTH 16 #define AC_ACCESS_REGISTER_REGNO (0xffffU << AC_ACCESS_REGISTER_REGNO_OFFSET) -#define AC_QUICK_ACCESS None /* -* This is 1 to indicate Quick Access command. + * This is 1 to indicate Quick Access command. */ #define AC_QUICK_ACCESS_CMDTYPE_OFFSET 24 #define AC_QUICK_ACCESS_CMDTYPE_LENGTH 8 #define AC_QUICK_ACCESS_CMDTYPE (0xffU << AC_QUICK_ACCESS_CMDTYPE_OFFSET) -#define AC_ACCESS_MEMORY None /* -* This is 2 to indicate Access Memory Command. + * This is 2 to indicate Access Memory Command. */ #define AC_ACCESS_MEMORY_CMDTYPE_OFFSET 24 #define AC_ACCESS_MEMORY_CMDTYPE_LENGTH 8 #define AC_ACCESS_MEMORY_CMDTYPE (0xffU << AC_ACCESS_MEMORY_CMDTYPE_OFFSET) /* -* An implementation does not have to implement both virtual and -* physical accesses, but it must fail accesses that it doesn't -* support. -* -* 0: Addresses are physical (to the hart they are performed on). -* -* 1: Addresses are virtual, and translated the way they would be from -* M-mode, with \Fmprv set. + * An implementation does not have to implement both virtual and + * physical accesses, but it must fail accesses that it doesn't + * support. + * + * 0: Addresses are physical (to the hart they are performed on). + * + * 1: Addresses are virtual, and translated the way they would be from + * M-mode, with \FcsrMcontrolMprv set. */ #define AC_ACCESS_MEMORY_AAMVIRTUAL_OFFSET 23 #define AC_ACCESS_MEMORY_AAMVIRTUAL_LENGTH 1 #define AC_ACCESS_MEMORY_AAMVIRTUAL (0x1U << AC_ACCESS_MEMORY_AAMVIRTUAL_OFFSET) /* -* 0: Access the lowest 8 bits of the memory location. -* -* 1: Access the lowest 16 bits of the memory location. -* -* 2: Access the lowest 32 bits of the memory location. -* -* 3: Access the lowest 64 bits of the memory location. -* -* 4: Access the lowest 128 bits of the memory location. + * 0: Access the lowest 8 bits of the memory location. + * + * 1: Access the lowest 16 bits of the memory location. + * + * 2: Access the lowest 32 bits of the memory location. + * + * 3: Access the lowest 64 bits of the memory location. + * + * 4: Access the lowest 128 bits of the memory location. */ #define AC_ACCESS_MEMORY_AAMSIZE_OFFSET 20 #define AC_ACCESS_MEMORY_AAMSIZE_LENGTH 3 #define AC_ACCESS_MEMORY_AAMSIZE (0x7U << AC_ACCESS_MEMORY_AAMSIZE_OFFSET) /* -* After a memory access has completed, if this bit is 1, increment -* {\tt arg1} (which contains the address used) by the number of bytes -* encoded in \Faamsize. + * After a memory access has completed, if this bit is 1, increment + * {\tt arg1} (which contains the address used) by the number of bytes + * encoded in \FacAccessmemoryAamsize. + * + * Supporting this variant is optional, but highly recommended for + * performance reasons. */ #define AC_ACCESS_MEMORY_AAMPOSTINCREMENT_OFFSET 19 #define AC_ACCESS_MEMORY_AAMPOSTINCREMENT_LENGTH 1 #define AC_ACCESS_MEMORY_AAMPOSTINCREMENT (0x1U << AC_ACCESS_MEMORY_AAMPOSTINCREMENT_OFFSET) /* -* 0: Copy data from the memory location specified in {\tt arg1} into -* the low bits of {\tt arg0}. Any remaining bits of {\tt arg0} now -* have an undefined value. -* -* 1: Copy data from the low bits of {\tt arg0} into the memory -* location specified in {\tt arg1}. + * 0: Copy data from the memory location specified in {\tt arg1} into + * the low bits of {\tt arg0}. Any remaining bits of {\tt arg0} now + * have an undefined value. + * + * 1: Copy data from the low bits of {\tt arg0} into the memory + * location specified in {\tt arg1}. */ #define AC_ACCESS_MEMORY_WRITE_OFFSET 16 #define AC_ACCESS_MEMORY_WRITE_LENGTH 1 #define AC_ACCESS_MEMORY_WRITE (0x1U << AC_ACCESS_MEMORY_WRITE_OFFSET) /* -* These bits are reserved for target-specific uses. + * These bits are reserved for target-specific uses. */ #define AC_ACCESS_MEMORY_TARGET_SPECIFIC_OFFSET 14 #define AC_ACCESS_MEMORY_TARGET_SPECIFIC_LENGTH 2 #define AC_ACCESS_MEMORY_TARGET_SPECIFIC (0x3U << AC_ACCESS_MEMORY_TARGET_SPECIFIC_OFFSET) #define VIRT_PRIV virtual /* -* Contains the privilege level the hart was operating in when Debug -* Mode was entered. The encoding is described in Table -* \ref{tab:privlevel}, and matches the privilege level encoding from -* the Privileged Spec. A user can write this -* value to change the hart's privilege level when exiting Debug Mode. + * Contains the privilege level the hart was operating in when Debug + * Mode was entered. The encoding is described in Table + * \ref{tab:privlevel}, and matches the privilege level encoding from + * the Privileged Spec. A user can write this + * value to change the hart's privilege level when exiting Debug Mode. */ #define VIRT_PRIV_PRV_OFFSET 0 #define VIRT_PRIV_PRV_LENGTH 2 #define VIRT_PRIV_PRV (0x3U << VIRT_PRIV_PRV_OFFSET) #define DMI_SERCS 0x34 /* -* Number of supported serial ports. + * Number of supported serial ports. */ #define DMI_SERCS_SERIALCOUNT_OFFSET 28 #define DMI_SERCS_SERIALCOUNT_LENGTH 4 #define DMI_SERCS_SERIALCOUNT (0xfU << DMI_SERCS_SERIALCOUNT_OFFSET) /* -* Select which serial port is accessed by \Rserrx and \Rsertx. + * Select which serial port is accessed by \RdmiSerrx and \RdmiSertx. */ #define DMI_SERCS_SERIAL_OFFSET 24 #define DMI_SERCS_SERIAL_LENGTH 3 @@ -1811,21 +1893,21 @@ #define DMI_SERCS_FULL1_LENGTH 1 #define DMI_SERCS_FULL1 (0x1U << DMI_SERCS_FULL1_OFFSET) /* -* 1 when the debugger-to-core queue for serial port 0 has -* over or underflowed. This bit will remain set until it is reset by -* writing 1 to this bit. + * 1 when the debugger-to-core queue for serial port 0 has + * over or underflowed. This bit will remain set until it is reset by + * writing 1 to this bit. */ #define DMI_SERCS_ERROR0_OFFSET 2 #define DMI_SERCS_ERROR0_LENGTH 1 #define DMI_SERCS_ERROR0 (0x1U << DMI_SERCS_ERROR0_OFFSET) /* -* 1 when the core-to-debugger queue for serial port 0 is not empty. + * 1 when the core-to-debugger queue for serial port 0 is not empty. */ #define DMI_SERCS_VALID0_OFFSET 1 #define DMI_SERCS_VALID0_LENGTH 1 #define DMI_SERCS_VALID0 (0x1U << DMI_SERCS_VALID0_OFFSET) /* -* 1 when the debugger-to-core queue for serial port 0 is full. + * 1 when the debugger-to-core queue for serial port 0 is full. */ #define DMI_SERCS_FULL0_OFFSET 0 #define DMI_SERCS_FULL0_LENGTH 1 diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 8a3adaf..28316bc 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -28,8 +28,8 @@ #include "asm.h" #include "batch.h" -#define DMI_DATA1 (DMI_DATA0 + 1) -#define DMI_PROGBUF1 (DMI_PROGBUF0 + 1) +#define DM_DATA1 (DM_DATA0 + 1) +#define DM_PROGBUF1 (DM_PROGBUF0 + 1) static int riscv013_on_step_or_resume(struct target *target, bool step); static int riscv013_step_or_resume_current_hart(struct target *target, @@ -285,14 +285,14 @@ dm013_info_t *get_dm(struct target *target) static uint32_t set_hartsel(uint32_t initial, uint32_t index) { - initial &= ~DMI_DMCONTROL_HARTSELLO; - initial &= ~DMI_DMCONTROL_HARTSELHI; + initial &= ~DM_DMCONTROL_HARTSELLO; + initial &= ~DM_DMCONTROL_HARTSELHI; - uint32_t index_lo = index & ((1 << DMI_DMCONTROL_HARTSELLO_LENGTH) - 1); - initial |= index_lo << DMI_DMCONTROL_HARTSELLO_OFFSET; - uint32_t index_hi = index >> DMI_DMCONTROL_HARTSELLO_LENGTH; - assert(index_hi < 1 << DMI_DMCONTROL_HARTSELHI_LENGTH); - initial |= index_hi << DMI_DMCONTROL_HARTSELHI_OFFSET; + uint32_t index_lo = index & ((1 << DM_DMCONTROL_HARTSELLO_LENGTH) - 1); + initial |= index_lo << DM_DMCONTROL_HARTSELLO_OFFSET; + uint32_t index_hi = index >> DM_DMCONTROL_HARTSELLO_LENGTH; + assert(index_hi < 1 << DM_DMCONTROL_HARTSELHI_LENGTH); + initial |= index_hi << DM_DMCONTROL_HARTSELHI_OFFSET; return initial; } @@ -304,56 +304,56 @@ static void decode_dmi(char *text, unsigned address, unsigned data) uint64_t mask; const char *name; } description[] = { - { DMI_DMCONTROL, DMI_DMCONTROL_HALTREQ, "haltreq" }, - { DMI_DMCONTROL, DMI_DMCONTROL_RESUMEREQ, "resumereq" }, - { DMI_DMCONTROL, DMI_DMCONTROL_HARTRESET, "hartreset" }, - { DMI_DMCONTROL, DMI_DMCONTROL_HASEL, "hasel" }, - { DMI_DMCONTROL, DMI_DMCONTROL_HARTSELHI, "hartselhi" }, - { DMI_DMCONTROL, DMI_DMCONTROL_HARTSELLO, "hartsello" }, - { DMI_DMCONTROL, DMI_DMCONTROL_NDMRESET, "ndmreset" }, - { DMI_DMCONTROL, DMI_DMCONTROL_DMACTIVE, "dmactive" }, - { DMI_DMCONTROL, DMI_DMCONTROL_ACKHAVERESET, "ackhavereset" }, - - { DMI_DMSTATUS, DMI_DMSTATUS_IMPEBREAK, "impebreak" }, - { DMI_DMSTATUS, DMI_DMSTATUS_ALLHAVERESET, "allhavereset" }, - { DMI_DMSTATUS, DMI_DMSTATUS_ANYHAVERESET, "anyhavereset" }, - { DMI_DMSTATUS, DMI_DMSTATUS_ALLRESUMEACK, "allresumeack" }, - { DMI_DMSTATUS, DMI_DMSTATUS_ANYRESUMEACK, "anyresumeack" }, - { DMI_DMSTATUS, DMI_DMSTATUS_ALLNONEXISTENT, "allnonexistent" }, - { DMI_DMSTATUS, DMI_DMSTATUS_ANYNONEXISTENT, "anynonexistent" }, - { DMI_DMSTATUS, DMI_DMSTATUS_ALLUNAVAIL, "allunavail" }, - { DMI_DMSTATUS, DMI_DMSTATUS_ANYUNAVAIL, "anyunavail" }, - { DMI_DMSTATUS, DMI_DMSTATUS_ALLRUNNING, "allrunning" }, - { DMI_DMSTATUS, DMI_DMSTATUS_ANYRUNNING, "anyrunning" }, - { DMI_DMSTATUS, DMI_DMSTATUS_ALLHALTED, "allhalted" }, - { DMI_DMSTATUS, DMI_DMSTATUS_ANYHALTED, "anyhalted" }, - { DMI_DMSTATUS, DMI_DMSTATUS_AUTHENTICATED, "authenticated" }, - { DMI_DMSTATUS, DMI_DMSTATUS_AUTHBUSY, "authbusy" }, - { DMI_DMSTATUS, DMI_DMSTATUS_HASRESETHALTREQ, "hasresethaltreq" }, - { DMI_DMSTATUS, DMI_DMSTATUS_CONFSTRPTRVALID, "confstrptrvalid" }, - { DMI_DMSTATUS, DMI_DMSTATUS_VERSION, "version" }, - - { DMI_ABSTRACTCS, DMI_ABSTRACTCS_PROGBUFSIZE, "progbufsize" }, - { DMI_ABSTRACTCS, DMI_ABSTRACTCS_BUSY, "busy" }, - { DMI_ABSTRACTCS, DMI_ABSTRACTCS_CMDERR, "cmderr" }, - { DMI_ABSTRACTCS, DMI_ABSTRACTCS_DATACOUNT, "datacount" }, - - { DMI_COMMAND, DMI_COMMAND_CMDTYPE, "cmdtype" }, - - { DMI_SBCS, DMI_SBCS_SBVERSION, "sbversion" }, - { DMI_SBCS, DMI_SBCS_SBBUSYERROR, "sbbusyerror" }, - { DMI_SBCS, DMI_SBCS_SBBUSY, "sbbusy" }, - { DMI_SBCS, DMI_SBCS_SBREADONADDR, "sbreadonaddr" }, - { DMI_SBCS, DMI_SBCS_SBACCESS, "sbaccess" }, - { DMI_SBCS, DMI_SBCS_SBAUTOINCREMENT, "sbautoincrement" }, - { DMI_SBCS, DMI_SBCS_SBREADONDATA, "sbreadondata" }, - { DMI_SBCS, DMI_SBCS_SBERROR, "sberror" }, - { DMI_SBCS, DMI_SBCS_SBASIZE, "sbasize" }, - { DMI_SBCS, DMI_SBCS_SBACCESS128, "sbaccess128" }, - { DMI_SBCS, DMI_SBCS_SBACCESS64, "sbaccess64" }, - { DMI_SBCS, DMI_SBCS_SBACCESS32, "sbaccess32" }, - { DMI_SBCS, DMI_SBCS_SBACCESS16, "sbaccess16" }, - { DMI_SBCS, DMI_SBCS_SBACCESS8, "sbaccess8" }, + { DM_DMCONTROL, DM_DMCONTROL_HALTREQ, "haltreq" }, + { DM_DMCONTROL, DM_DMCONTROL_RESUMEREQ, "resumereq" }, + { DM_DMCONTROL, DM_DMCONTROL_HARTRESET, "hartreset" }, + { DM_DMCONTROL, DM_DMCONTROL_HASEL, "hasel" }, + { DM_DMCONTROL, DM_DMCONTROL_HARTSELHI, "hartselhi" }, + { DM_DMCONTROL, DM_DMCONTROL_HARTSELLO, "hartsello" }, + { DM_DMCONTROL, DM_DMCONTROL_NDMRESET, "ndmreset" }, + { DM_DMCONTROL, DM_DMCONTROL_DMACTIVE, "dmactive" }, + { DM_DMCONTROL, DM_DMCONTROL_ACKHAVERESET, "ackhavereset" }, + + { DM_DMSTATUS, DM_DMSTATUS_IMPEBREAK, "impebreak" }, + { DM_DMSTATUS, DM_DMSTATUS_ALLHAVERESET, "allhavereset" }, + { DM_DMSTATUS, DM_DMSTATUS_ANYHAVERESET, "anyhavereset" }, + { DM_DMSTATUS, DM_DMSTATUS_ALLRESUMEACK, "allresumeack" }, + { DM_DMSTATUS, DM_DMSTATUS_ANYRESUMEACK, "anyresumeack" }, + { DM_DMSTATUS, DM_DMSTATUS_ALLNONEXISTENT, "allnonexistent" }, + { DM_DMSTATUS, DM_DMSTATUS_ANYNONEXISTENT, "anynonexistent" }, + { DM_DMSTATUS, DM_DMSTATUS_ALLUNAVAIL, "allunavail" }, + { DM_DMSTATUS, DM_DMSTATUS_ANYUNAVAIL, "anyunavail" }, + { DM_DMSTATUS, DM_DMSTATUS_ALLRUNNING, "allrunning" }, + { DM_DMSTATUS, DM_DMSTATUS_ANYRUNNING, "anyrunning" }, + { DM_DMSTATUS, DM_DMSTATUS_ALLHALTED, "allhalted" }, + { DM_DMSTATUS, DM_DMSTATUS_ANYHALTED, "anyhalted" }, + { DM_DMSTATUS, DM_DMSTATUS_AUTHENTICATED, "authenticated" }, + { DM_DMSTATUS, DM_DMSTATUS_AUTHBUSY, "authbusy" }, + { DM_DMSTATUS, DM_DMSTATUS_HASRESETHALTREQ, "hasresethaltreq" }, + { DM_DMSTATUS, DM_DMSTATUS_CONFSTRPTRVALID, "confstrptrvalid" }, + { DM_DMSTATUS, DM_DMSTATUS_VERSION, "version" }, + + { DM_ABSTRACTCS, DM_ABSTRACTCS_PROGBUFSIZE, "progbufsize" }, + { DM_ABSTRACTCS, DM_ABSTRACTCS_BUSY, "busy" }, + { DM_ABSTRACTCS, DM_ABSTRACTCS_CMDERR, "cmderr" }, + { DM_ABSTRACTCS, DM_ABSTRACTCS_DATACOUNT, "datacount" }, + + { DM_COMMAND, DM_COMMAND_CMDTYPE, "cmdtype" }, + + { DM_SBCS, DM_SBCS_SBVERSION, "sbversion" }, + { DM_SBCS, DM_SBCS_SBBUSYERROR, "sbbusyerror" }, + { DM_SBCS, DM_SBCS_SBBUSY, "sbbusy" }, + { DM_SBCS, DM_SBCS_SBREADONADDR, "sbreadonaddr" }, + { DM_SBCS, DM_SBCS_SBACCESS, "sbaccess" }, + { DM_SBCS, DM_SBCS_SBAUTOINCREMENT, "sbautoincrement" }, + { DM_SBCS, DM_SBCS_SBREADONDATA, "sbreadondata" }, + { DM_SBCS, DM_SBCS_SBERROR, "sberror" }, + { DM_SBCS, DM_SBCS_SBASIZE, "sbasize" }, + { DM_SBCS, DM_SBCS_SBACCESS128, "sbaccess128" }, + { DM_SBCS, DM_SBCS_SBACCESS64, "sbaccess64" }, + { DM_SBCS, DM_SBCS_SBACCESS32, "sbaccess32" }, + { DM_SBCS, DM_SBCS_SBACCESS16, "sbaccess16" }, + { DM_SBCS, DM_SBCS_SBACCESS8, "sbaccess8" }, }; text[0] = 0; @@ -684,16 +684,16 @@ int dmstatus_read_timeout(struct target *target, uint32_t *dmstatus, bool authenticated, unsigned timeout_sec) { int result = dmi_op_timeout(target, dmstatus, NULL, DMI_OP_READ, - DMI_DMSTATUS, 0, timeout_sec, false, true); + DM_DMSTATUS, 0, timeout_sec, false, true); if (result != ERROR_OK) return result; - int dmstatus_version = get_field(*dmstatus, DMI_DMSTATUS_VERSION); + int dmstatus_version = get_field(*dmstatus, DM_DMSTATUS_VERSION); if (dmstatus_version != 2 && dmstatus_version != 3) { LOG_ERROR("OpenOCD only supports Debug Module version 2 (0.13) and 3 (0.14), not " "%d (dmstatus=0x%x). This error might be caused by a JTAG " "signal issue. Try reducing the JTAG clock speed.", - get_field(*dmstatus, DMI_DMSTATUS_VERSION), *dmstatus); - } else if (authenticated && !get_field(*dmstatus, DMI_DMSTATUS_AUTHENTICATED)) { + get_field(*dmstatus, DM_DMSTATUS_VERSION), *dmstatus); + } else if (authenticated && !get_field(*dmstatus, DM_DMSTATUS_AUTHENTICATED)) { LOG_ERROR("Debugger is not authenticated to target Debug Module. " "(dmstatus=0x%x). Use `riscv authdata_read` and " "`riscv authdata_write` commands to authenticate.", *dmstatus); @@ -738,14 +738,14 @@ static int wait_for_idle(struct target *target, uint32_t *abstractcs) RISCV013_INFO(info); time_t start = time(NULL); while (1) { - if (dmi_read(target, abstractcs, DMI_ABSTRACTCS) != ERROR_OK) + if (dmi_read(target, abstractcs, DM_ABSTRACTCS) != ERROR_OK) return ERROR_FAIL; - if (get_field(*abstractcs, DMI_ABSTRACTCS_BUSY) == 0) + if (get_field(*abstractcs, DM_ABSTRACTCS_BUSY) == 0) return ERROR_OK; if (time(NULL) - start > riscv_command_timeout_sec) { - info->cmderr = get_field(*abstractcs, DMI_ABSTRACTCS_CMDERR); + info->cmderr = get_field(*abstractcs, DM_ABSTRACTCS_CMDERR); if (info->cmderr != CMDERR_NONE) { const char *errors[8] = { "none", @@ -774,7 +774,7 @@ static int execute_abstract_command(struct target *target, uint32_t command) { RISCV013_INFO(info); if (debug_level >= LOG_LVL_DEBUG) { - switch (get_field(command, DMI_COMMAND_CMDTYPE)) { + switch (get_field(command, DM_COMMAND_CMDTYPE)) { case 0: LOG_DEBUG("command=0x%x; access register, size=%d, postexec=%d, " "transfer=%d, write=%d, regno=0x%x", @@ -791,17 +791,17 @@ static int execute_abstract_command(struct target *target, uint32_t command) } } - if (dmi_write_exec(target, DMI_COMMAND, command, false) != ERROR_OK) + if (dmi_write_exec(target, DM_COMMAND, command, false) != ERROR_OK) return ERROR_FAIL; uint32_t abstractcs = 0; int result = wait_for_idle(target, &abstractcs); - info->cmderr = get_field(abstractcs, DMI_ABSTRACTCS_CMDERR); + info->cmderr = get_field(abstractcs, DM_ABSTRACTCS_CMDERR); if (info->cmderr != 0 || result != ERROR_OK) { LOG_DEBUG("command 0x%x failed; abstractcs=0x%x", command, abstractcs); /* Clear the error. */ - dmi_write(target, DMI_ABSTRACTCS, DMI_ABSTRACTCS_CMDERR); + dmi_write(target, DM_ABSTRACTCS, DM_ABSTRACTCS_CMDERR); return ERROR_FAIL; } @@ -819,11 +819,11 @@ static riscv_reg_t read_abstract_arg(struct target *target, unsigned index, LOG_ERROR("Unsupported size: %d bits", size_bits); return ~0; case 64: - dmi_read(target, &v, DMI_DATA0 + offset + 1); + dmi_read(target, &v, DM_DATA0 + offset + 1); value |= ((uint64_t) v) << 32; /* falls through */ case 32: - dmi_read(target, &v, DMI_DATA0 + offset); + dmi_read(target, &v, DM_DATA0 + offset); value |= v; } return value; @@ -838,10 +838,10 @@ static int write_abstract_arg(struct target *target, unsigned index, LOG_ERROR("Unsupported size: %d bits", size_bits); return ERROR_FAIL; case 64: - dmi_write(target, DMI_DATA0 + offset + 1, value >> 32); + dmi_write(target, DM_DATA0 + offset + 1, value >> 32); /* falls through */ case 32: - dmi_write(target, DMI_DATA0 + offset, value); + dmi_write(target, DM_DATA0 + offset, value); } return ERROR_OK; } @@ -852,7 +852,7 @@ static int write_abstract_arg(struct target *target, unsigned index, static uint32_t access_register_command(struct target *target, uint32_t number, unsigned size, uint32_t flags) { - uint32_t command = set_field(0, DMI_COMMAND_CMDTYPE, 0); + uint32_t command = set_field(0, DM_COMMAND_CMDTYPE, 0); switch (size) { case 32: command = set_field(command, AC_ACCESS_REGISTER_AARSIZE, 2); @@ -1047,7 +1047,7 @@ static int examine_progbuf(struct target *target) } uint32_t written; - if (dmi_read(target, &written, DMI_PROGBUF0) != ERROR_OK) + if (dmi_read(target, &written, DM_PROGBUF0) != ERROR_OK) return ERROR_FAIL; if (written == (uint32_t) info->progbuf_address) { LOG_INFO("progbuf is writable at 0x%" PRIx64, @@ -1114,7 +1114,7 @@ static int cleanup_after_register_access(struct target *target, } typedef enum { - SPACE_DMI_DATA, + SPACE_DM_DATA, SPACE_DMI_PROGBUF, SPACE_DMI_RAM } memory_space_t; @@ -1156,7 +1156,7 @@ static int scratch_reserve(struct target *target, if ((size_bytes + scratch->hart_address - info->dataaddr + 3) / 4 >= info->datasize) { - scratch->memory_space = SPACE_DMI_DATA; + scratch->memory_space = SPACE_DM_DATA; scratch->debug_address = (scratch->hart_address - info->dataaddr) / 4; return ERROR_OK; } @@ -1207,19 +1207,19 @@ static int scratch_read64(struct target *target, scratch_mem_t *scratch, { uint32_t v; switch (scratch->memory_space) { - case SPACE_DMI_DATA: - if (dmi_read(target, &v, DMI_DATA0 + scratch->debug_address) != ERROR_OK) + case SPACE_DM_DATA: + if (dmi_read(target, &v, DM_DATA0 + scratch->debug_address) != ERROR_OK) return ERROR_FAIL; *value = v; - if (dmi_read(target, &v, DMI_DATA1 + scratch->debug_address) != ERROR_OK) + if (dmi_read(target, &v, DM_DATA1 + scratch->debug_address) != ERROR_OK) return ERROR_FAIL; *value |= ((uint64_t) v) << 32; break; case SPACE_DMI_PROGBUF: - if (dmi_read(target, &v, DMI_PROGBUF0 + scratch->debug_address) != ERROR_OK) + if (dmi_read(target, &v, DM_PROGBUF0 + scratch->debug_address) != ERROR_OK) return ERROR_FAIL; *value = v; - if (dmi_read(target, &v, DMI_PROGBUF1 + scratch->debug_address) != ERROR_OK) + if (dmi_read(target, &v, DM_PROGBUF1 + scratch->debug_address) != ERROR_OK) return ERROR_FAIL; *value |= ((uint64_t) v) << 32; break; @@ -1246,13 +1246,13 @@ static int scratch_write64(struct target *target, scratch_mem_t *scratch, uint64_t value) { switch (scratch->memory_space) { - case SPACE_DMI_DATA: - dmi_write(target, DMI_DATA0 + scratch->debug_address, value); - dmi_write(target, DMI_DATA1 + scratch->debug_address, value >> 32); + case SPACE_DM_DATA: + dmi_write(target, DM_DATA0 + scratch->debug_address, value); + dmi_write(target, DM_DATA1 + scratch->debug_address, value >> 32); break; case SPACE_DMI_PROGBUF: - dmi_write(target, DMI_PROGBUF0 + scratch->debug_address, value); - dmi_write(target, DMI_PROGBUF1 + scratch->debug_address, value >> 32); + dmi_write(target, DM_PROGBUF0 + scratch->debug_address, value); + dmi_write(target, DM_PROGBUF1 + scratch->debug_address, value >> 32); break; case SPACE_DMI_RAM: { @@ -1506,7 +1506,7 @@ int wait_for_authbusy(struct target *target, uint32_t *dmstatus) return ERROR_FAIL; if (dmstatus) *dmstatus = value; - if (!get_field(value, DMI_DMSTATUS_AUTHBUSY)) + if (!get_field(value, DM_DMSTATUS_AUTHBUSY)) break; if (time(NULL) - start > riscv_command_timeout_sec) { LOG_ERROR("Timed out after %ds waiting for authbusy to go low (dmstatus=0x%x). " @@ -1533,13 +1533,13 @@ static void deinit_target(struct target *target) static int set_haltgroup(struct target *target, bool *supported) { - uint32_t write = set_field(DMI_DMCS2_HGWRITE, DMI_DMCS2_HALTGROUP, target->smp); - if (dmi_write(target, DMI_DMCS2, write) != ERROR_OK) + uint32_t write = set_field(DM_DMCS2_HGWRITE, DM_DMCS2_GROUP, target->smp); + if (dmi_write(target, DM_DMCS2, write) != ERROR_OK) return ERROR_FAIL; uint32_t read; - if (dmi_read(target, &read, DMI_DMCS2) != ERROR_OK) + if (dmi_read(target, &read, DM_DMCS2) != ERROR_OK) return ERROR_FAIL; - *supported = get_field(read, DMI_DMCS2_HALTGROUP) == (unsigned)target->smp; + *supported = get_field(read, DM_DMCS2_GROUP) == (unsigned)target->smp; return ERROR_OK; } @@ -1591,40 +1591,40 @@ static int examine(struct target *target) /* Reset the Debug Module. */ dm013_info_t *dm = get_dm(target); if (!dm->was_reset) { - dmi_write(target, DMI_DMCONTROL, 0); - dmi_write(target, DMI_DMCONTROL, DMI_DMCONTROL_DMACTIVE); + dmi_write(target, DM_DMCONTROL, 0); + dmi_write(target, DM_DMCONTROL, DM_DMCONTROL_DMACTIVE); dm->was_reset = true; } - dmi_write(target, DMI_DMCONTROL, DMI_DMCONTROL_HARTSELLO | - DMI_DMCONTROL_HARTSELHI | DMI_DMCONTROL_DMACTIVE | - DMI_DMCONTROL_HASEL); + dmi_write(target, DM_DMCONTROL, DM_DMCONTROL_HARTSELLO | + DM_DMCONTROL_HARTSELHI | DM_DMCONTROL_DMACTIVE | + DM_DMCONTROL_HASEL); uint32_t dmcontrol; - if (dmi_read(target, &dmcontrol, DMI_DMCONTROL) != ERROR_OK) + if (dmi_read(target, &dmcontrol, DM_DMCONTROL) != ERROR_OK) return ERROR_FAIL; - if (!get_field(dmcontrol, DMI_DMCONTROL_DMACTIVE)) { + if (!get_field(dmcontrol, DM_DMCONTROL_DMACTIVE)) { LOG_ERROR("Debug Module did not become active. dmcontrol=0x%x", dmcontrol); return ERROR_FAIL; } - dm->hasel_supported = get_field(dmcontrol, DMI_DMCONTROL_HASEL); + dm->hasel_supported = get_field(dmcontrol, DM_DMCONTROL_HASEL); uint32_t dmstatus; if (dmstatus_read(target, &dmstatus, false) != ERROR_OK) return ERROR_FAIL; LOG_DEBUG("dmstatus: 0x%08x", dmstatus); - int dmstatus_version = get_field(dmstatus, DMI_DMSTATUS_VERSION); + int dmstatus_version = get_field(dmstatus, DM_DMSTATUS_VERSION); if (dmstatus_version != 2 && dmstatus_version != 3) { /* Error was already printed out in dmstatus_read(). */ return ERROR_FAIL; } uint32_t hartsel = - (get_field(dmcontrol, DMI_DMCONTROL_HARTSELHI) << - DMI_DMCONTROL_HARTSELLO_LENGTH) | - get_field(dmcontrol, DMI_DMCONTROL_HARTSELLO); + (get_field(dmcontrol, DM_DMCONTROL_HARTSELHI) << + DM_DMCONTROL_HARTSELLO_LENGTH) | + get_field(dmcontrol, DM_DMCONTROL_HARTSELLO); info->hartsellen = 0; while (hartsel & 1) { info->hartsellen++; @@ -1633,14 +1633,14 @@ static int examine(struct target *target) LOG_DEBUG("hartsellen=%d", info->hartsellen); uint32_t hartinfo; - if (dmi_read(target, &hartinfo, DMI_HARTINFO) != ERROR_OK) + if (dmi_read(target, &hartinfo, DM_HARTINFO) != ERROR_OK) return ERROR_FAIL; - info->datasize = get_field(hartinfo, DMI_HARTINFO_DATASIZE); - info->dataaccess = get_field(hartinfo, DMI_HARTINFO_DATAACCESS); - info->dataaddr = get_field(hartinfo, DMI_HARTINFO_DATAADDR); + info->datasize = get_field(hartinfo, DM_HARTINFO_DATASIZE); + info->dataaccess = get_field(hartinfo, DM_HARTINFO_DATAACCESS); + info->dataaddr = get_field(hartinfo, DM_HARTINFO_DATAADDR); - if (!get_field(dmstatus, DMI_DMSTATUS_AUTHENTICATED)) { + if (!get_field(dmstatus, DM_DMSTATUS_AUTHENTICATED)) { LOG_ERROR("Debugger is not authenticated to target Debug Module. " "(dmstatus=0x%x). Use `riscv authdata_read` and " "`riscv authdata_write` commands to authenticate.", dmstatus); @@ -1651,20 +1651,20 @@ static int examine(struct target *target) return ERROR_OK; } - if (dmi_read(target, &info->sbcs, DMI_SBCS) != ERROR_OK) + if (dmi_read(target, &info->sbcs, DM_SBCS) != ERROR_OK) return ERROR_FAIL; /* Check that abstract data registers are accessible. */ uint32_t abstractcs; - if (dmi_read(target, &abstractcs, DMI_ABSTRACTCS) != ERROR_OK) + if (dmi_read(target, &abstractcs, DM_ABSTRACTCS) != ERROR_OK) return ERROR_FAIL; - info->datacount = get_field(abstractcs, DMI_ABSTRACTCS_DATACOUNT); - info->progbufsize = get_field(abstractcs, DMI_ABSTRACTCS_PROGBUFSIZE); + info->datacount = get_field(abstractcs, DM_ABSTRACTCS_DATACOUNT); + info->progbufsize = get_field(abstractcs, DM_ABSTRACTCS_PROGBUFSIZE); LOG_INFO("datacount=%d progbufsize=%d", info->datacount, info->progbufsize); RISCV_INFO(r); - r->impebreak = get_field(dmstatus, DMI_DMSTATUS_IMPEBREAK); + r->impebreak = get_field(dmstatus, DM_DMSTATUS_IMPEBREAK); if (!has_sufficient_progbuf(target, 2)) { LOG_WARNING("We won't be able to execute fence instructions on this " @@ -1690,13 +1690,13 @@ static int examine(struct target *target) uint32_t s; if (dmstatus_read(target, &s, true) != ERROR_OK) return ERROR_FAIL; - if (get_field(s, DMI_DMSTATUS_ANYNONEXISTENT)) + if (get_field(s, DM_DMSTATUS_ANYNONEXISTENT)) break; dm->hart_count = i + 1; - if (get_field(s, DMI_DMSTATUS_ANYHAVERESET)) - dmi_write(target, DMI_DMCONTROL, - set_hartsel(DMI_DMCONTROL_DMACTIVE | DMI_DMCONTROL_ACKHAVERESET, i)); + if (get_field(s, DM_DMSTATUS_ANYHAVERESET)) + dmi_write(target, DM_DMCONTROL, + set_hartsel(DM_DMCONTROL_DMACTIVE | DM_DMCONTROL_ACKHAVERESET, i)); } LOG_DEBUG("Detected %d harts.", dm->hart_count); @@ -1793,7 +1793,7 @@ int riscv013_authdata_read(struct target *target, uint32_t *value) if (wait_for_authbusy(target, NULL) != ERROR_OK) return ERROR_FAIL; - return dmi_read(target, value, DMI_AUTHDATA); + return dmi_read(target, value, DM_AUTHDATA); } int riscv013_authdata_write(struct target *target, uint32_t value) @@ -1802,13 +1802,13 @@ int riscv013_authdata_write(struct target *target, uint32_t value) if (wait_for_authbusy(target, &before) != ERROR_OK) return ERROR_FAIL; - dmi_write(target, DMI_AUTHDATA, value); + dmi_write(target, DM_AUTHDATA, value); if (wait_for_authbusy(target, &after) != ERROR_OK) return ERROR_FAIL; - if (!get_field(before, DMI_DMSTATUS_AUTHENTICATED) && - get_field(after, DMI_DMSTATUS_AUTHENTICATED)) { + if (!get_field(before, DM_DMSTATUS_AUTHENTICATED) && + get_field(after, DM_DMSTATUS_AUTHENTICATED)) { LOG_INFO("authdata_write resulted in successful authentication"); int result = ERROR_OK; dm013_info_t *dm = get_dm(target); @@ -1838,15 +1838,15 @@ static unsigned riscv013_data_bits(struct target *target) if (has_sufficient_progbuf(target, 3) && !riscv_prefer_sba) return riscv_xlen(target); - if (get_field(info->sbcs, DMI_SBCS_SBACCESS128)) + if (get_field(info->sbcs, DM_SBCS_SBACCESS128)) return 128; - if (get_field(info->sbcs, DMI_SBCS_SBACCESS64)) + if (get_field(info->sbcs, DM_SBCS_SBACCESS64)) return 64; - if (get_field(info->sbcs, DMI_SBCS_SBACCESS32)) + if (get_field(info->sbcs, DM_SBCS_SBACCESS32)) return 32; - if (get_field(info->sbcs, DMI_SBCS_SBACCESS16)) + if (get_field(info->sbcs, DM_SBCS_SBACCESS16)) return 16; - if (get_field(info->sbcs, DMI_SBCS_SBACCESS8)) + if (get_field(info->sbcs, DM_SBCS_SBACCESS8)) return 8; return riscv_xlen(target); @@ -2066,7 +2066,7 @@ static int assert_reset(struct target *target) select_dmi(target); - uint32_t control_base = set_field(0, DMI_DMCONTROL_DMACTIVE, 1); + uint32_t control_base = set_field(0, DM_DMCONTROL_DMACTIVE, 1); if (target->rtos) { /* There's only one target, and OpenOCD thinks each hart is a thread. @@ -2081,21 +2081,21 @@ static int assert_reset(struct target *target) continue; control = set_hartsel(control_base, i); - control = set_field(control, DMI_DMCONTROL_HALTREQ, + control = set_field(control, DM_DMCONTROL_HALTREQ, target->reset_halt ? 1 : 0); - dmi_write(target, DMI_DMCONTROL, control); + dmi_write(target, DM_DMCONTROL, control); } /* Assert ndmreset */ - control = set_field(control, DMI_DMCONTROL_NDMRESET, 1); - dmi_write(target, DMI_DMCONTROL, control); + control = set_field(control, DM_DMCONTROL_NDMRESET, 1); + dmi_write(target, DM_DMCONTROL, control); } else { /* Reset just this hart. */ uint32_t control = set_hartsel(control_base, r->current_hartid); - control = set_field(control, DMI_DMCONTROL_HALTREQ, + control = set_field(control, DM_DMCONTROL_HALTREQ, target->reset_halt ? 1 : 0); - control = set_field(control, DMI_DMCONTROL_NDMRESET, 1); - dmi_write(target, DMI_DMCONTROL, control); + control = set_field(control, DM_DMCONTROL_NDMRESET, 1); + dmi_write(target, DM_DMCONTROL, control); } target->state = TARGET_RESET; @@ -2118,9 +2118,9 @@ static int deassert_reset(struct target *target) /* Clear the reset, but make sure haltreq is still set */ uint32_t control = 0; - control = set_field(control, DMI_DMCONTROL_HALTREQ, target->reset_halt ? 1 : 0); - control = set_field(control, DMI_DMCONTROL_DMACTIVE, 1); - dmi_write(target, DMI_DMCONTROL, + control = set_field(control, DM_DMCONTROL_HALTREQ, target->reset_halt ? 1 : 0); + control = set_field(control, DM_DMCONTROL_DMACTIVE, 1); + dmi_write(target, DM_DMCONTROL, set_hartsel(control, r->current_hartid)); uint32_t dmstatus; @@ -2132,7 +2132,7 @@ static int deassert_reset(struct target *target) if (target->rtos) { if (!riscv_hart_enabled(target, index)) continue; - dmi_write(target, DMI_DMCONTROL, + dmi_write(target, DM_DMCONTROL, set_hartsel(control, index)); } else { index = r->current_hartid; @@ -2142,10 +2142,10 @@ static int deassert_reset(struct target *target) uint32_t expected_field; if (target->reset_halt) { operation = "halt"; - expected_field = DMI_DMSTATUS_ALLHALTED; + expected_field = DM_DMSTATUS_ALLHALTED; } else { operation = "run"; - expected_field = DMI_DMSTATUS_ALLRUNNING; + expected_field = DM_DMSTATUS_ALLRUNNING; } LOG_DEBUG("Waiting for hart %d to %s out of reset.", index, operation); while (1) { @@ -2170,11 +2170,11 @@ static int deassert_reset(struct target *target) } target->state = TARGET_HALTED; - if (get_field(dmstatus, DMI_DMSTATUS_ALLHAVERESET)) { + if (get_field(dmstatus, DM_DMSTATUS_ALLHAVERESET)) { /* Ack reset. */ - dmi_write(target, DMI_DMCONTROL, + dmi_write(target, DM_DMCONTROL, set_hartsel(control, index) | - DMI_DMCONTROL_ACKHAVERESET); + DM_DMCONTROL_ACKHAVERESET); } if (!target->rtos) @@ -2316,7 +2316,7 @@ static int read_memory_bus_word(struct target *target, target_addr_t address, { uint32_t value; int result; - static int sbdata[4] = { DMI_SBDATA0, DMI_SBDATA1, DMI_SBDATA2, DMI_SBDATA3 }; + static int sbdata[4] = { DM_SBDATA0, DM_SBDATA1, DM_SBDATA2, DM_SBDATA3 }; assert(size <= 16); for (int i = (size - 1) / 4; i >= 0; i--) { result = dmi_op(target, &value, NULL, DMI_OP_READ, sbdata[i], 0, false, true); @@ -2332,15 +2332,15 @@ static uint32_t sb_sbaccess(unsigned size_bytes) { switch (size_bytes) { case 1: - return set_field(0, DMI_SBCS_SBACCESS, 0); + return set_field(0, DM_SBCS_SBACCESS, 0); case 2: - return set_field(0, DMI_SBCS_SBACCESS, 1); + return set_field(0, DM_SBCS_SBACCESS, 1); case 4: - return set_field(0, DMI_SBCS_SBACCESS, 2); + return set_field(0, DM_SBCS_SBACCESS, 2); case 8: - return set_field(0, DMI_SBCS_SBACCESS, 3); + return set_field(0, DM_SBCS_SBACCESS, 3); case 16: - return set_field(0, DMI_SBCS_SBACCESS, 4); + return set_field(0, DM_SBCS_SBACCESS, 4); } assert(0); return 0; /* Make mingw happy. */ @@ -2349,15 +2349,15 @@ static uint32_t sb_sbaccess(unsigned size_bytes) static target_addr_t sb_read_address(struct target *target) { RISCV013_INFO(info); - unsigned sbasize = get_field(info->sbcs, DMI_SBCS_SBASIZE); + unsigned sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE); target_addr_t address = 0; uint32_t v; if (sbasize > 32) { - dmi_read(target, &v, DMI_SBADDRESS1); + dmi_read(target, &v, DM_SBADDRESS1); address |= v; address <<= 32; } - dmi_read(target, &v, DMI_SBADDRESS0); + dmi_read(target, &v, DM_SBADDRESS0); address |= v; return address; } @@ -2365,24 +2365,24 @@ static target_addr_t sb_read_address(struct target *target) static int sb_write_address(struct target *target, target_addr_t address) { RISCV013_INFO(info); - unsigned sbasize = get_field(info->sbcs, DMI_SBCS_SBASIZE); + unsigned sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE); /* There currently is no support for >64-bit addresses in OpenOCD. */ if (sbasize > 96) - dmi_write(target, DMI_SBADDRESS3, 0); + dmi_write(target, DM_SBADDRESS3, 0); if (sbasize > 64) - dmi_write(target, DMI_SBADDRESS2, 0); + dmi_write(target, DM_SBADDRESS2, 0); if (sbasize > 32) - dmi_write(target, DMI_SBADDRESS1, address >> 32); - return dmi_write(target, DMI_SBADDRESS0, address); + dmi_write(target, DM_SBADDRESS1, address >> 32); + return dmi_write(target, DM_SBADDRESS0, address); } static int read_sbcs_nonbusy(struct target *target, uint32_t *sbcs) { time_t start = time(NULL); while (1) { - if (dmi_read(target, sbcs, DMI_SBCS) != ERROR_OK) + if (dmi_read(target, sbcs, DM_SBCS) != ERROR_OK) return ERROR_FAIL; - if (!get_field(*sbcs, DMI_SBCS_SBBUSY)) + if (!get_field(*sbcs, DM_SBCS_SBBUSY)) return ERROR_OK; if (time(NULL) - start > riscv_command_timeout_sec) { LOG_ERROR("Timed out after %ds waiting for sbbusy to go low (sbcs=0x%x). " @@ -2439,26 +2439,26 @@ static int read_memory_bus_v0(struct target *target, target_addr_t address, riscv_addr_t fin_addr = address + (count * size); uint32_t access = 0; - const int DMI_SBCS_SBSINGLEREAD_OFFSET = 20; - const uint32_t DMI_SBCS_SBSINGLEREAD = (0x1U << DMI_SBCS_SBSINGLEREAD_OFFSET); + const int DM_SBCS_SBSINGLEREAD_OFFSET = 20; + const uint32_t DM_SBCS_SBSINGLEREAD = (0x1U << DM_SBCS_SBSINGLEREAD_OFFSET); - const int DMI_SBCS_SBAUTOREAD_OFFSET = 15; - const uint32_t DMI_SBCS_SBAUTOREAD = (0x1U << DMI_SBCS_SBAUTOREAD_OFFSET); + const int DM_SBCS_SBAUTOREAD_OFFSET = 15; + const uint32_t DM_SBCS_SBAUTOREAD = (0x1U << DM_SBCS_SBAUTOREAD_OFFSET); /* ww favorise one off reading if there is an issue */ if (count == 1) { for (uint32_t i = 0; i < count; i++) { - if (dmi_read(target, &access, DMI_SBCS) != ERROR_OK) + if (dmi_read(target, &access, DM_SBCS) != ERROR_OK) return ERROR_FAIL; - dmi_write(target, DMI_SBADDRESS0, cur_addr); + dmi_write(target, DM_SBADDRESS0, cur_addr); /* size/2 matching the bit access of the spec 0.13 */ - access = set_field(access, DMI_SBCS_SBACCESS, size/2); - access = set_field(access, DMI_SBCS_SBSINGLEREAD, 1); + access = set_field(access, DM_SBCS_SBACCESS, size/2); + access = set_field(access, DM_SBCS_SBSINGLEREAD, 1); LOG_DEBUG("\r\nread_memory: sab: access: 0x%08x", access); - dmi_write(target, DMI_SBCS, access); + dmi_write(target, DM_SBCS, access); /* 3) read */ uint32_t value; - if (dmi_read(target, &value, DMI_SBDATA0) != ERROR_OK) + if (dmi_read(target, &value, DM_SBDATA0) != ERROR_OK) return ERROR_FAIL; LOG_DEBUG("\r\nread_memory: sab: value: 0x%08x", value); write_to_buf(t_buffer, value, size); @@ -2470,25 +2470,25 @@ static int read_memory_bus_v0(struct target *target, target_addr_t address, /* has to be the same size if we want to read a block */ LOG_DEBUG("reading block until final address 0x%" PRIx64, fin_addr); - if (dmi_read(target, &access, DMI_SBCS) != ERROR_OK) + if (dmi_read(target, &access, DM_SBCS) != ERROR_OK) return ERROR_FAIL; /* set current address */ - dmi_write(target, DMI_SBADDRESS0, cur_addr); + dmi_write(target, DM_SBADDRESS0, cur_addr); /* 2) write sbaccess=2, sbsingleread,sbautoread,sbautoincrement * size/2 matching the bit access of the spec 0.13 */ - access = set_field(access, DMI_SBCS_SBACCESS, size/2); - access = set_field(access, DMI_SBCS_SBAUTOREAD, 1); - access = set_field(access, DMI_SBCS_SBSINGLEREAD, 1); - access = set_field(access, DMI_SBCS_SBAUTOINCREMENT, 1); + access = set_field(access, DM_SBCS_SBACCESS, size/2); + access = set_field(access, DM_SBCS_SBAUTOREAD, 1); + access = set_field(access, DM_SBCS_SBSINGLEREAD, 1); + access = set_field(access, DM_SBCS_SBAUTOINCREMENT, 1); LOG_DEBUG("\r\naccess: 0x%08x", access); - dmi_write(target, DMI_SBCS, access); + dmi_write(target, DM_SBCS, access); while (cur_addr < fin_addr) { LOG_DEBUG("\r\nsab:autoincrement: \r\n size: %d\tcount:%d\taddress: 0x%08" PRIx64, size, count, cur_addr); /* read */ uint32_t value; - if (dmi_read(target, &value, DMI_SBDATA0) != ERROR_OK) + if (dmi_read(target, &value, DM_SBDATA0) != ERROR_OK) return ERROR_FAIL; write_to_buf(t_buffer, value, size); cur_addr += size; @@ -2496,8 +2496,8 @@ static int read_memory_bus_v0(struct target *target, target_addr_t address, /* if we are reaching last address, we must clear autoread */ if (cur_addr == fin_addr && count != 1) { - dmi_write(target, DMI_SBCS, 0); - if (dmi_read(target, &value, DMI_SBDATA0) != ERROR_OK) + dmi_write(target, DM_SBCS, 0); + if (dmi_read(target, &value, DM_SBDATA0) != ERROR_OK) return ERROR_FAIL; write_to_buf(t_buffer, value, size); } @@ -2522,13 +2522,13 @@ static int read_memory_bus_v1(struct target *target, target_addr_t address, target_addr_t end_address = address + count * size; while (next_address < end_address) { - uint32_t sbcs_write = set_field(0, DMI_SBCS_SBREADONADDR, 1); + uint32_t sbcs_write = set_field(0, DM_SBCS_SBREADONADDR, 1); sbcs_write |= sb_sbaccess(size); if (increment == size) - sbcs_write = set_field(sbcs_write, DMI_SBCS_SBAUTOINCREMENT, 1); + sbcs_write = set_field(sbcs_write, DM_SBCS_SBAUTOINCREMENT, 1); if (count > 1) - sbcs_write = set_field(sbcs_write, DMI_SBCS_SBREADONDATA, count > 1); - if (dmi_write(target, DMI_SBCS, sbcs_write) != ERROR_OK) + sbcs_write = set_field(sbcs_write, DM_SBCS_SBREADONDATA, count > 1); + if (dmi_write(target, DM_SBCS, sbcs_write) != ERROR_OK) return ERROR_FAIL; /* This address write will trigger the first read. */ @@ -2546,7 +2546,7 @@ static int read_memory_bus_v1(struct target *target, target_addr_t address, /* First value has been read, and is waiting for us to issue a DMI read * to get it. */ - static int sbdata[4] = {DMI_SBDATA0, DMI_SBDATA1, DMI_SBDATA2, DMI_SBDATA3}; + static int sbdata[4] = {DM_SBDATA0, DM_SBDATA1, DM_SBDATA2, DM_SBDATA3}; assert(size <= 16); target_addr_t next_read = address - 1; for (uint32_t i = (next_address - address) / size; i < count - 1; i++) { @@ -2602,14 +2602,14 @@ static int read_memory_bus_v1(struct target *target, target_addr_t address, if (read_sbcs_nonbusy(target, &sbcs_read) != ERROR_OK) return ERROR_FAIL; - sbcs_write = set_field(sbcs_write, DMI_SBCS_SBREADONDATA, 0); - if (dmi_write(target, DMI_SBCS, sbcs_write) != ERROR_OK) + sbcs_write = set_field(sbcs_write, DM_SBCS_SBREADONDATA, 0); + if (dmi_write(target, DM_SBCS, sbcs_write) != ERROR_OK) return ERROR_FAIL; } /* Read the last word, after we disabled sbreadondata if necessary. */ - if (!get_field(sbcs_read, DMI_SBCS_SBERROR) && - !get_field(sbcs_read, DMI_SBCS_SBBUSYERROR)) { + if (!get_field(sbcs_read, DM_SBCS_SBERROR) && + !get_field(sbcs_read, DM_SBCS_SBBUSYERROR)) { if (read_memory_bus_word(target, address + (count - 1) * size, size, buffer + (count - 1) * size) != ERROR_OK) return ERROR_FAIL; @@ -2618,22 +2618,22 @@ static int read_memory_bus_v1(struct target *target, target_addr_t address, return ERROR_FAIL; } - if (get_field(sbcs_read, DMI_SBCS_SBBUSYERROR)) { + if (get_field(sbcs_read, DM_SBCS_SBBUSYERROR)) { /* We read while the target was busy. Slow down and try again. */ - if (dmi_write(target, DMI_SBCS, DMI_SBCS_SBBUSYERROR) != ERROR_OK) + if (dmi_write(target, DM_SBCS, DM_SBCS_SBBUSYERROR) != ERROR_OK) return ERROR_FAIL; next_address = sb_read_address(target); info->bus_master_read_delay += info->bus_master_read_delay / 10 + 1; continue; } - unsigned error = get_field(sbcs_read, DMI_SBCS_SBERROR); + unsigned error = get_field(sbcs_read, DM_SBCS_SBERROR); if (error == 0) { next_address = end_address; } else { /* Some error indicating the bus access failed, but not because of * something we did wrong. */ - if (dmi_write(target, DMI_SBCS, DMI_SBCS_SBERROR) != ERROR_OK) + if (dmi_write(target, DM_SBCS, DM_SBCS_SBERROR) != ERROR_OK) return ERROR_FAIL; return ERROR_FAIL; } @@ -2819,13 +2819,13 @@ static int read_memory_progbuf_inner(struct target *target, target_addr_t addres return ERROR_OK; } - if (dmi_write(target, DMI_ABSTRACTAUTO, - 1 << DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET) != ERROR_OK) + if (dmi_write(target, DM_ABSTRACTAUTO, + 1 << DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET) != ERROR_OK) goto error; /* Read garbage from dmi_data0, which triggers another execution of the * program. Now dmi_data0 contains the first good result, and s1 the next * memory value. */ - if (dmi_read_exec(target, NULL, DMI_DATA0) != ERROR_OK) + if (dmi_read_exec(target, NULL, DM_DATA0) != ERROR_OK) goto error; /* read_addr is the next address that the hart will read from, which is the @@ -2848,8 +2848,8 @@ static int read_memory_progbuf_inner(struct target *target, target_addr_t addres unsigned reads = 0; for (unsigned j = index; j < count; j++) { if (size > 4) - riscv_batch_add_dmi_read(batch, DMI_DATA1); - riscv_batch_add_dmi_read(batch, DMI_DATA0); + riscv_batch_add_dmi_read(batch, DM_DATA1); + riscv_batch_add_dmi_read(batch, DM_DATA0); reads++; if (riscv_batch_full(batch)) @@ -2862,12 +2862,12 @@ static int read_memory_progbuf_inner(struct target *target, target_addr_t addres * and update our copy of cmderr. If we see that DMI is busy here, * dmi_busy_delay will be incremented. */ uint32_t abstractcs; - if (dmi_read(target, &abstractcs, DMI_ABSTRACTCS) != ERROR_OK) + if (dmi_read(target, &abstractcs, DM_ABSTRACTCS) != ERROR_OK) return ERROR_FAIL; - while (get_field(abstractcs, DMI_ABSTRACTCS_BUSY)) - if (dmi_read(target, &abstractcs, DMI_ABSTRACTCS) != ERROR_OK) + while (get_field(abstractcs, DM_ABSTRACTCS_BUSY)) + if (dmi_read(target, &abstractcs, DM_ABSTRACTCS) != ERROR_OK) return ERROR_FAIL; - info->cmderr = get_field(abstractcs, DMI_ABSTRACTCS_CMDERR); + info->cmderr = get_field(abstractcs, DM_ABSTRACTCS_CMDERR); unsigned next_index; unsigned ignore_last = 0; @@ -2882,17 +2882,17 @@ static int read_memory_progbuf_inner(struct target *target, target_addr_t addres increase_ac_busy_delay(target); riscv013_clear_abstract_error(target); - dmi_write(target, DMI_ABSTRACTAUTO, 0); + dmi_write(target, DM_ABSTRACTAUTO, 0); uint32_t dmi_data0, dmi_data1 = 0; /* This is definitely a good version of the value that we * attempted to read when we discovered that the target was * busy. */ - if (dmi_read(target, &dmi_data0, DMI_DATA0) != ERROR_OK) { + if (dmi_read(target, &dmi_data0, DM_DATA0) != ERROR_OK) { riscv_batch_free(batch); goto error; } - if (size > 4 && dmi_read(target, &dmi_data1, DMI_DATA1) != ERROR_OK) { + if (size > 4 && dmi_read(target, &dmi_data1, DM_DATA1) != ERROR_OK) { riscv_batch_free(batch); goto error; } @@ -2918,13 +2918,13 @@ static int read_memory_progbuf_inner(struct target *target, target_addr_t addres log_memory_access(address + (next_index - 2) * size, value64, size, true); /* Restore the command, and execute it. - * Now DMI_DATA0 contains the next value just as it would if no + * Now DM_DATA0 contains the next value just as it would if no * error had occurred. */ - dmi_write_exec(target, DMI_COMMAND, command, true); + dmi_write_exec(target, DM_COMMAND, command, true); next_index++; - dmi_write(target, DMI_ABSTRACTAUTO, - 1 << DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET); + dmi_write(target, DM_ABSTRACTAUTO, + 1 << DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET); ignore_last = 1; @@ -2989,14 +2989,14 @@ static int read_memory_progbuf_inner(struct target *target, target_addr_t addres riscv_batch_free(batch); } - dmi_write(target, DMI_ABSTRACTAUTO, 0); + dmi_write(target, DM_ABSTRACTAUTO, 0); if (count > 1) { /* Read the penultimate word. */ uint32_t dmi_data0, dmi_data1 = 0; - if (dmi_read(target, &dmi_data0, DMI_DATA0) != ERROR_OK) + if (dmi_read(target, &dmi_data0, DM_DATA0) != ERROR_OK) return ERROR_FAIL; - if (size > 4 && dmi_read(target, &dmi_data1, DMI_DATA1) != ERROR_OK) + if (size > 4 && dmi_read(target, &dmi_data1, DM_DATA1) != ERROR_OK) return ERROR_FAIL; uint64_t value64 = (((uint64_t)dmi_data1) << 32) | dmi_data0; write_to_buf(buffer + size * (count - 2), value64, size); @@ -3014,7 +3014,7 @@ static int read_memory_progbuf_inner(struct target *target, target_addr_t addres return ERROR_OK; error: - dmi_write(target, DMI_ABSTRACTAUTO, 0); + dmi_write(target, DM_ABSTRACTAUTO, 0); return result; } @@ -3222,15 +3222,15 @@ static int read_memory(struct target *target, target_addr_t address, return read_memory_progbuf(target, address, size, count, buffer, increment); - if ((get_field(info->sbcs, DMI_SBCS_SBACCESS8) && size == 1) || - (get_field(info->sbcs, DMI_SBCS_SBACCESS16) && size == 2) || - (get_field(info->sbcs, DMI_SBCS_SBACCESS32) && size == 4) || - (get_field(info->sbcs, DMI_SBCS_SBACCESS64) && size == 8) || - (get_field(info->sbcs, DMI_SBCS_SBACCESS128) && size == 16)) { - if (get_field(info->sbcs, DMI_SBCS_SBVERSION) == 0) + if ((get_field(info->sbcs, DM_SBCS_SBACCESS8) && size == 1) || + (get_field(info->sbcs, DM_SBCS_SBACCESS16) && size == 2) || + (get_field(info->sbcs, DM_SBCS_SBACCESS32) && size == 4) || + (get_field(info->sbcs, DM_SBCS_SBACCESS64) && size == 8) || + (get_field(info->sbcs, DM_SBCS_SBACCESS128) && size == 16)) { + if (get_field(info->sbcs, DM_SBCS_SBVERSION) == 0) return read_memory_bus_v0(target, address, size, count, buffer, increment); - else if (get_field(info->sbcs, DMI_SBCS_SBVERSION) == 1) + else if (get_field(info->sbcs, DM_SBCS_SBVERSION) == 1) return read_memory_bus_v1(target, address, size, count, buffer, increment); } @@ -3249,7 +3249,7 @@ static int write_memory_bus_v0(struct target *target, target_addr_t address, /*1) write sbaddress: for singlewrite and autoincrement, we need to write the address once*/ LOG_DEBUG("System Bus Access: size: %d\tcount:%d\tstart address: 0x%08" TARGET_PRIxADDR, size, count, address); - dmi_write(target, DMI_SBADDRESS0, address); + dmi_write(target, DM_SBADDRESS0, address); int64_t value = 0; int64_t access = 0; riscv_addr_t offset = 0; @@ -3280,21 +3280,21 @@ static int write_memory_bus_v0(struct target *target, target_addr_t address, } access = 0; - access = set_field(access, DMI_SBCS_SBACCESS, size/2); - dmi_write(target, DMI_SBCS, access); + access = set_field(access, DM_SBCS_SBACCESS, size/2); + dmi_write(target, DM_SBCS, access); LOG_DEBUG("\r\naccess: 0x%08" PRIx64, access); LOG_DEBUG("\r\nwrite_memory:SAB: ONE OFF: value 0x%08" PRIx64, value); - dmi_write(target, DMI_SBDATA0, value); + dmi_write(target, DM_SBDATA0, value); return ERROR_OK; } /*B.8 Writing Memory, using autoincrement*/ access = 0; - access = set_field(access, DMI_SBCS_SBACCESS, size/2); - access = set_field(access, DMI_SBCS_SBAUTOINCREMENT, 1); + access = set_field(access, DM_SBCS_SBACCESS, size/2); + access = set_field(access, DM_SBCS_SBAUTOINCREMENT, 1); LOG_DEBUG("\r\naccess: 0x%08" PRIx64, access); - dmi_write(target, DMI_SBCS, access); + dmi_write(target, DM_SBCS, access); /*2)set the value according to the size required and write*/ for (riscv_addr_t i = 0; i < count; ++i) { @@ -3324,11 +3324,11 @@ static int write_memory_bus_v0(struct target *target, target_addr_t address, } LOG_DEBUG("SAB:autoincrement: expected address: 0x%08x value: 0x%08x" PRIx64, (uint32_t)t_addr, (uint32_t)value); - dmi_write(target, DMI_SBDATA0, value); + dmi_write(target, DM_SBDATA0, value); } /*reset the autoincrement when finished (something weird is happening if this is not done at the end*/ - access = set_field(access, DMI_SBCS_SBAUTOINCREMENT, 0); - dmi_write(target, DMI_SBCS, access); + access = set_field(access, DM_SBCS_SBAUTOINCREMENT, 0); + dmi_write(target, DM_SBCS, access); return ERROR_OK; } @@ -3338,8 +3338,8 @@ static int write_memory_bus_v1(struct target *target, target_addr_t address, { RISCV013_INFO(info); uint32_t sbcs = sb_sbaccess(size); - sbcs = set_field(sbcs, DMI_SBCS_SBAUTOINCREMENT, 1); - dmi_write(target, DMI_SBCS, sbcs); + sbcs = set_field(sbcs, DM_SBCS_SBAUTOINCREMENT, 1); + dmi_write(target, DM_SBCS, sbcs); target_addr_t next_address = address; target_addr_t end_address = address + count * size; @@ -3363,20 +3363,20 @@ static int write_memory_bus_v1(struct target *target, target_addr_t address, break; if (size > 12) - riscv_batch_add_dmi_write(batch, DMI_SBDATA3, + riscv_batch_add_dmi_write(batch, DM_SBDATA3, ((uint32_t) p[12]) | (((uint32_t) p[13]) << 8) | (((uint32_t) p[14]) << 16) | (((uint32_t) p[15]) << 24)); if (size > 8) - riscv_batch_add_dmi_write(batch, DMI_SBDATA2, + riscv_batch_add_dmi_write(batch, DM_SBDATA2, ((uint32_t) p[8]) | (((uint32_t) p[9]) << 8) | (((uint32_t) p[10]) << 16) | (((uint32_t) p[11]) << 24)); if (size > 4) - riscv_batch_add_dmi_write(batch, DMI_SBDATA1, + riscv_batch_add_dmi_write(batch, DM_SBDATA1, ((uint32_t) p[4]) | (((uint32_t) p[5]) << 8) | (((uint32_t) p[6]) << 16) | @@ -3388,7 +3388,7 @@ static int write_memory_bus_v1(struct target *target, target_addr_t address, } if (size > 1) value |= ((uint32_t) p[1]) << 8; - riscv_batch_add_dmi_write(batch, DMI_SBDATA0, value); + riscv_batch_add_dmi_write(batch, DM_SBDATA0, value); log_memory_access(address + i * size, value, size, false); next_address += size; @@ -3401,12 +3401,12 @@ static int write_memory_bus_v1(struct target *target, target_addr_t address, bool dmi_busy_encountered; if (dmi_op(target, &sbcs, &dmi_busy_encountered, DMI_OP_READ, - DMI_SBCS, 0, false, false) != ERROR_OK) + DM_SBCS, 0, false, false) != ERROR_OK) return ERROR_FAIL; time_t start = time(NULL); bool dmi_busy = dmi_busy_encountered; - while (get_field(sbcs, DMI_SBCS_SBBUSY) || dmi_busy) { + while (get_field(sbcs, DM_SBCS_SBBUSY) || dmi_busy) { if (time(NULL) - start > riscv_command_timeout_sec) { LOG_ERROR("Timed out after %ds waiting for sbbusy to go low (sbcs=0x%x). " "Increase the timeout with riscv set_command_timeout_sec.", @@ -3415,17 +3415,17 @@ static int write_memory_bus_v1(struct target *target, target_addr_t address, } if (dmi_op(target, &sbcs, &dmi_busy, DMI_OP_READ, - DMI_SBCS, 0, false, true) != ERROR_OK) + DM_SBCS, 0, false, true) != ERROR_OK) return ERROR_FAIL; } - if (get_field(sbcs, DMI_SBCS_SBBUSYERROR)) { + if (get_field(sbcs, DM_SBCS_SBBUSYERROR)) { /* We wrote while the target was busy. Slow down and try again. */ - dmi_write(target, DMI_SBCS, DMI_SBCS_SBBUSYERROR); + dmi_write(target, DM_SBCS, DM_SBCS_SBBUSYERROR); info->bus_master_write_delay += info->bus_master_write_delay / 10 + 1; } - if (get_field(sbcs, DMI_SBCS_SBBUSYERROR) || dmi_busy_encountered) { + if (get_field(sbcs, DM_SBCS_SBBUSYERROR) || dmi_busy_encountered) { next_address = sb_read_address(target); if (next_address < address) { /* This should never happen, probably buggy hardware. */ @@ -3437,11 +3437,11 @@ static int write_memory_bus_v1(struct target *target, target_addr_t address, continue; } - unsigned error = get_field(sbcs, DMI_SBCS_SBERROR); + unsigned error = get_field(sbcs, DM_SBCS_SBERROR); if (error != 0) { /* Some error indicating the bus access failed, but not because of * something we did wrong. */ - dmi_write(target, DMI_SBCS, DMI_SBCS_SBERROR); + dmi_write(target, DM_SBCS, DM_SBCS_SBERROR); return ERROR_FAIL; } } @@ -3548,8 +3548,8 @@ static int write_memory_progbuf(struct target *target, target_addr_t address, /* Write value. */ if (size > 4) - dmi_write(target, DMI_DATA1, value >> 32); - dmi_write(target, DMI_DATA0, value); + dmi_write(target, DM_DATA1, value >> 32); + dmi_write(target, DM_DATA0, value); /* Write and execute command that moves value into S1 and * executes program buffer. */ @@ -3565,14 +3565,14 @@ static int write_memory_progbuf(struct target *target, target_addr_t address, } /* Turn on autoexec */ - dmi_write(target, DMI_ABSTRACTAUTO, - 1 << DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET); + dmi_write(target, DM_ABSTRACTAUTO, + 1 << DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET); setup_needed = false; } else { if (size > 4) - riscv_batch_add_dmi_write(batch, DMI_DATA1, value >> 32); - riscv_batch_add_dmi_write(batch, DMI_DATA0, value); + riscv_batch_add_dmi_write(batch, DM_DATA1, value >> 32); + riscv_batch_add_dmi_write(batch, DM_DATA0, value); if (riscv_batch_full(batch)) break; } @@ -3590,13 +3590,13 @@ static int write_memory_progbuf(struct target *target, target_addr_t address, uint32_t abstractcs; bool dmi_busy_encountered; result = dmi_op(target, &abstractcs, &dmi_busy_encountered, - DMI_OP_READ, DMI_ABSTRACTCS, 0, false, true); + DMI_OP_READ, DM_ABSTRACTCS, 0, false, true); if (result != ERROR_OK) goto error; - while (get_field(abstractcs, DMI_ABSTRACTCS_BUSY)) - if (dmi_read(target, &abstractcs, DMI_ABSTRACTCS) != ERROR_OK) + while (get_field(abstractcs, DM_ABSTRACTCS_BUSY)) + if (dmi_read(target, &abstractcs, DM_ABSTRACTCS) != ERROR_OK) return ERROR_FAIL; - info->cmderr = get_field(abstractcs, DMI_ABSTRACTCS_CMDERR); + info->cmderr = get_field(abstractcs, DM_ABSTRACTCS_CMDERR); if (info->cmderr == CMDERR_NONE && !dmi_busy_encountered) { LOG_DEBUG("successful (partial?) memory write"); } else if (info->cmderr == CMDERR_BUSY || dmi_busy_encountered) { @@ -3607,7 +3607,7 @@ static int write_memory_progbuf(struct target *target, target_addr_t address, riscv013_clear_abstract_error(target); increase_ac_busy_delay(target); - dmi_write(target, DMI_ABSTRACTAUTO, 0); + dmi_write(target, DM_ABSTRACTAUTO, 0); result = register_read_direct(target, &cur_addr, GDB_REGNO_S0); if (result != ERROR_OK) goto error; @@ -3621,7 +3621,7 @@ static int write_memory_progbuf(struct target *target, target_addr_t address, } error: - dmi_write(target, DMI_ABSTRACTAUTO, 0); + dmi_write(target, DM_ABSTRACTAUTO, 0); if (register_write_direct(target, GDB_REGNO_S1, s1) != ERROR_OK) return ERROR_FAIL; @@ -3647,14 +3647,14 @@ static int write_memory(struct target *target, target_addr_t address, if (has_sufficient_progbuf(target, 3) && !riscv_prefer_sba) return write_memory_progbuf(target, address, size, count, buffer); - if ((get_field(info->sbcs, DMI_SBCS_SBACCESS8) && size == 1) || - (get_field(info->sbcs, DMI_SBCS_SBACCESS16) && size == 2) || - (get_field(info->sbcs, DMI_SBCS_SBACCESS32) && size == 4) || - (get_field(info->sbcs, DMI_SBCS_SBACCESS64) && size == 8) || - (get_field(info->sbcs, DMI_SBCS_SBACCESS128) && size == 16)) { - if (get_field(info->sbcs, DMI_SBCS_SBVERSION) == 0) + if ((get_field(info->sbcs, DM_SBCS_SBACCESS8) && size == 1) || + (get_field(info->sbcs, DM_SBCS_SBACCESS16) && size == 2) || + (get_field(info->sbcs, DM_SBCS_SBACCESS32) && size == 4) || + (get_field(info->sbcs, DM_SBCS_SBACCESS64) && size == 8) || + (get_field(info->sbcs, DM_SBCS_SBACCESS128) && size == 16)) { + if (get_field(info->sbcs, DM_SBCS_SBVERSION) == 0) return write_memory_bus_v0(target, address, size, count, buffer); - else if (get_field(info->sbcs, DMI_SBCS_SBVERSION) == 1) + else if (get_field(info->sbcs, DM_SBCS_SBVERSION) == 1) return write_memory_bus_v1(target, address, size, count, buffer); } @@ -3758,10 +3758,10 @@ static int riscv013_select_current_hart(struct target *target) uint32_t dmcontrol; /* TODO: can't we just "dmcontrol = DMI_DMACTIVE"? */ - if (dmi_read(target, &dmcontrol, DMI_DMCONTROL) != ERROR_OK) + if (dmi_read(target, &dmcontrol, DM_DMCONTROL) != ERROR_OK) return ERROR_FAIL; dmcontrol = set_hartsel(dmcontrol, r->current_hartid); - int result = dmi_write(target, DMI_DMCONTROL, dmcontrol); + int result = dmi_write(target, DM_DMCONTROL, dmcontrol); dm->current_hartid = r->current_hartid; return result; } @@ -3808,9 +3808,9 @@ static int select_prepped_harts(struct target *target, bool *use_hasel) } for (unsigned i = 0; i < hawindow_count; i++) { - if (dmi_write(target, DMI_HAWINDOWSEL, i) != ERROR_OK) + if (dmi_write(target, DM_HAWINDOWSEL, i) != ERROR_OK) return ERROR_FAIL; - if (dmi_write(target, DMI_HAWINDOW, hawindow[i]) != ERROR_OK) + if (dmi_write(target, DM_HAWINDOW, hawindow[i]) != ERROR_OK) return ERROR_FAIL; } @@ -3835,11 +3835,11 @@ static int riscv013_halt_go(struct target *target) LOG_DEBUG("halting hart %d", r->current_hartid); /* Issue the halt command, and then wait for the current hart to halt. */ - uint32_t dmcontrol = DMI_DMCONTROL_DMACTIVE | DMI_DMCONTROL_HALTREQ; + uint32_t dmcontrol = DM_DMCONTROL_DMACTIVE | DM_DMCONTROL_HALTREQ; if (use_hasel) - dmcontrol |= DMI_DMCONTROL_HASEL; + dmcontrol |= DM_DMCONTROL_HASEL; dmcontrol = set_hartsel(dmcontrol, r->current_hartid); - dmi_write(target, DMI_DMCONTROL, dmcontrol); + dmi_write(target, DM_DMCONTROL, dmcontrol); for (size_t i = 0; i < 256; ++i) if (riscv_is_halted(target)) break; @@ -3848,7 +3848,7 @@ static int riscv013_halt_go(struct target *target) uint32_t dmstatus; if (dmstatus_read(target, &dmstatus, true) != ERROR_OK) return ERROR_FAIL; - if (dmi_read(target, &dmcontrol, DMI_DMCONTROL) != ERROR_OK) + if (dmi_read(target, &dmcontrol, DM_DMCONTROL) != ERROR_OK) return ERROR_FAIL; LOG_ERROR("unable to halt hart %d", r->current_hartid); @@ -3857,8 +3857,8 @@ static int riscv013_halt_go(struct target *target) return ERROR_FAIL; } - dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_HALTREQ, 0); - dmi_write(target, DMI_DMCONTROL, dmcontrol); + dmcontrol = set_field(dmcontrol, DM_DMCONTROL_HALTREQ, 0); + dmi_write(target, DM_DMCONTROL, dmcontrol); if (use_hasel) { target_list_t *entry; @@ -3911,16 +3911,16 @@ static bool riscv013_is_halted(struct target *target) uint32_t dmstatus; if (dmstatus_read(target, &dmstatus, true) != ERROR_OK) return false; - if (get_field(dmstatus, DMI_DMSTATUS_ANYUNAVAIL)) + if (get_field(dmstatus, DM_DMSTATUS_ANYUNAVAIL)) LOG_ERROR("Hart %d is unavailable.", riscv_current_hartid(target)); - if (get_field(dmstatus, DMI_DMSTATUS_ANYNONEXISTENT)) + if (get_field(dmstatus, DM_DMSTATUS_ANYNONEXISTENT)) LOG_ERROR("Hart %d doesn't exist.", riscv_current_hartid(target)); - if (get_field(dmstatus, DMI_DMSTATUS_ANYHAVERESET)) { + if (get_field(dmstatus, DM_DMSTATUS_ANYHAVERESET)) { int hartid = riscv_current_hartid(target); LOG_INFO("Hart %d unexpectedly reset!", hartid); /* TODO: Can we make this more obvious to eg. a gdb user? */ - uint32_t dmcontrol = DMI_DMCONTROL_DMACTIVE | - DMI_DMCONTROL_ACKHAVERESET; + uint32_t dmcontrol = DM_DMCONTROL_DMACTIVE | + DM_DMCONTROL_ACKHAVERESET; dmcontrol = set_hartsel(dmcontrol, hartid); /* If we had been halted when we reset, request another halt. If we * ended up running out of reset, then the user will (hopefully) get a @@ -3928,10 +3928,10 @@ static bool riscv013_is_halted(struct target *target) * that it is halted again once the request goes through. */ if (target->state == TARGET_HALTED) - dmcontrol |= DMI_DMCONTROL_HALTREQ; - dmi_write(target, DMI_DMCONTROL, dmcontrol); + dmcontrol |= DM_DMCONTROL_HALTREQ; + dmi_write(target, DM_DMCONTROL, dmcontrol); } - return get_field(dmstatus, DMI_DMSTATUS_ALLHALTED); + return get_field(dmstatus, DM_DMSTATUS_ALLHALTED); } static enum riscv_halt_reason riscv013_halt_reason(struct target *target) @@ -3969,7 +3969,7 @@ int riscv013_write_debug_buffer(struct target *target, unsigned index, riscv_ins { dm013_info_t *dm = get_dm(target); if (dm->progbuf_cache[index] != data) { - if (dmi_write(target, DMI_PROGBUF0 + index, data) != ERROR_OK) + if (dmi_write(target, DM_PROGBUF0 + index, data) != ERROR_OK) return ERROR_FAIL; dm->progbuf_cache[index] = data; } else { @@ -3981,7 +3981,7 @@ int riscv013_write_debug_buffer(struct target *target, unsigned index, riscv_ins riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned index) { uint32_t value; - dmi_read(target, &value, DMI_PROGBUF0 + index); + dmi_read(target, &value, DM_PROGBUF0 + index); return value; } @@ -4025,11 +4025,11 @@ static int get_max_sbaccess(struct target *target) { RISCV013_INFO(info); - uint32_t sbaccess128 = get_field(info->sbcs, DMI_SBCS_SBACCESS128); - uint32_t sbaccess64 = get_field(info->sbcs, DMI_SBCS_SBACCESS64); - uint32_t sbaccess32 = get_field(info->sbcs, DMI_SBCS_SBACCESS32); - uint32_t sbaccess16 = get_field(info->sbcs, DMI_SBCS_SBACCESS16); - uint32_t sbaccess8 = get_field(info->sbcs, DMI_SBCS_SBACCESS8); + uint32_t sbaccess128 = get_field(info->sbcs, DM_SBCS_SBACCESS128); + uint32_t sbaccess64 = get_field(info->sbcs, DM_SBCS_SBACCESS64); + uint32_t sbaccess32 = get_field(info->sbcs, DM_SBCS_SBACCESS32); + uint32_t sbaccess16 = get_field(info->sbcs, DM_SBCS_SBACCESS16); + uint32_t sbaccess8 = get_field(info->sbcs, DM_SBCS_SBACCESS8); if (sbaccess128) return 4; @@ -4049,9 +4049,9 @@ static uint32_t get_num_sbdata_regs(struct target *target) { RISCV013_INFO(info); - uint32_t sbaccess128 = get_field(info->sbcs, DMI_SBCS_SBACCESS128); - uint32_t sbaccess64 = get_field(info->sbcs, DMI_SBCS_SBACCESS64); - uint32_t sbaccess32 = get_field(info->sbcs, DMI_SBCS_SBACCESS32); + uint32_t sbaccess128 = get_field(info->sbcs, DM_SBCS_SBACCESS128); + uint32_t sbaccess64 = get_field(info->sbcs, DM_SBCS_SBACCESS64); + uint32_t sbaccess32 = get_field(info->sbcs, DM_SBCS_SBACCESS32); if (sbaccess128) return 4; @@ -4073,7 +4073,7 @@ static int riscv013_test_sba_config_reg(struct target *target, uint32_t rd_val; uint32_t sbcs_orig; - dmi_read(target, &sbcs_orig, DMI_SBCS); + dmi_read(target, &sbcs_orig, DM_SBCS); uint32_t sbcs = sbcs_orig; bool test_passed; @@ -4085,9 +4085,9 @@ static int riscv013_test_sba_config_reg(struct target *target, return ERROR_FAIL; } - if (get_field(sbcs, DMI_SBCS_SBVERSION) != 1) { + if (get_field(sbcs, DM_SBCS_SBVERSION) != 1) { LOG_ERROR("System Bus Access unsupported SBVERSION (%d). Only version 1 is supported.", - get_field(sbcs, DMI_SBCS_SBVERSION)); + get_field(sbcs, DM_SBCS_SBVERSION)); return ERROR_FAIL; } @@ -4097,13 +4097,13 @@ static int riscv013_test_sba_config_reg(struct target *target, /* Test 1: Simple write/read test */ test_passed = true; - sbcs = set_field(sbcs_orig, DMI_SBCS_SBAUTOINCREMENT, 0); - dmi_write(target, DMI_SBCS, sbcs); + sbcs = set_field(sbcs_orig, DM_SBCS_SBAUTOINCREMENT, 0); + dmi_write(target, DM_SBCS, sbcs); uint32_t test_patterns[4] = {0xdeadbeef, 0xfeedbabe, 0x12345678, 0x08675309}; for (uint32_t sbaccess = 0; sbaccess <= (uint32_t)max_sbaccess; sbaccess++) { - sbcs = set_field(sbcs, DMI_SBCS_SBACCESS, sbaccess); - dmi_write(target, DMI_SBCS, sbcs); + sbcs = set_field(sbcs, DM_SBCS_SBACCESS, sbaccess); + dmi_write(target, DM_SBCS, sbcs); uint32_t compare_mask = (sbaccess == 0) ? 0xff : (sbaccess == 1) ? 0xffff : 0xffffffff; @@ -4135,14 +4135,14 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t curr_addr; target_addr_t prev_addr; test_passed = true; - sbcs = set_field(sbcs_orig, DMI_SBCS_SBAUTOINCREMENT, 1); - dmi_write(target, DMI_SBCS, sbcs); + sbcs = set_field(sbcs_orig, DM_SBCS_SBAUTOINCREMENT, 1); + dmi_write(target, DM_SBCS, sbcs); for (uint32_t sbaccess = 0; sbaccess <= (uint32_t)max_sbaccess; sbaccess++) { - sbcs = set_field(sbcs, DMI_SBCS_SBACCESS, sbaccess); - dmi_write(target, DMI_SBCS, sbcs); + sbcs = set_field(sbcs, DM_SBCS_SBACCESS, sbaccess); + dmi_write(target, DM_SBCS, sbcs); - dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DM_SBADDRESS0, legal_address); read_sbcs_nonbusy(target, &sbcs); curr_addr = legal_address; for (uint32_t i = 0; i < num_words; i++) { @@ -4154,17 +4154,17 @@ static int riscv013_test_sba_config_reg(struct target *target, test_passed = false; tests_failed++; } - dmi_write(target, DMI_SBDATA0, i); + dmi_write(target, DM_SBDATA0, i); } read_sbcs_nonbusy(target, &sbcs); - dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DM_SBADDRESS0, legal_address); uint32_t val; - sbcs = set_field(sbcs, DMI_SBCS_SBREADONDATA, 1); - dmi_write(target, DMI_SBCS, sbcs); - dmi_read(target, &val, DMI_SBDATA0); /* Dummy read to trigger first system bus read */ + sbcs = set_field(sbcs, DM_SBCS_SBREADONDATA, 1); + dmi_write(target, DM_SBCS, sbcs); + dmi_read(target, &val, DM_SBDATA0); /* Dummy read to trigger first system bus read */ curr_addr = legal_address; for (uint32_t i = 0; i < num_words; i++) { prev_addr = curr_addr; @@ -4175,7 +4175,7 @@ static int riscv013_test_sba_config_reg(struct target *target, test_passed = false; tests_failed++; } - dmi_read(target, &val, DMI_SBDATA0); + dmi_read(target, &val, DM_SBDATA0); read_sbcs_nonbusy(target, &sbcs); if (i != val) { LOG_ERROR("System Bus Access Test 2: Error reading auto-incremented address," @@ -4191,12 +4191,12 @@ static int riscv013_test_sba_config_reg(struct target *target, /* Test 3: Read from illegal address */ read_memory_sba_simple(target, illegal_address, rd_buf, 1, sbcs_orig); - dmi_read(target, &rd_val, DMI_SBCS); - if (get_field(rd_val, DMI_SBCS_SBERROR) == 2) { - sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 2); - dmi_write(target, DMI_SBCS, sbcs); - dmi_read(target, &rd_val, DMI_SBCS); - if (get_field(rd_val, DMI_SBCS_SBERROR) == 0) + dmi_read(target, &rd_val, DM_SBCS); + if (get_field(rd_val, DM_SBCS_SBERROR) == 2) { + sbcs = set_field(sbcs_orig, DM_SBCS_SBERROR, 2); + dmi_write(target, DM_SBCS, sbcs); + dmi_read(target, &rd_val, DM_SBCS); + if (get_field(rd_val, DM_SBCS_SBERROR) == 0) LOG_INFO("System Bus Access Test 3: Illegal address read test PASSED."); else LOG_ERROR("System Bus Access Test 3: Illegal address read test FAILED, unable to clear to 0."); @@ -4207,12 +4207,12 @@ static int riscv013_test_sba_config_reg(struct target *target, /* Test 4: Write to illegal address */ write_memory_sba_simple(target, illegal_address, test_patterns, 1, sbcs_orig); - dmi_read(target, &rd_val, DMI_SBCS); - if (get_field(rd_val, DMI_SBCS_SBERROR) == 2) { - sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 2); - dmi_write(target, DMI_SBCS, sbcs); - dmi_read(target, &rd_val, DMI_SBCS); - if (get_field(rd_val, DMI_SBCS_SBERROR) == 0) + dmi_read(target, &rd_val, DM_SBCS); + if (get_field(rd_val, DM_SBCS_SBERROR) == 2) { + sbcs = set_field(sbcs_orig, DM_SBCS_SBERROR, 2); + dmi_write(target, DM_SBCS, sbcs); + dmi_read(target, &rd_val, DM_SBCS); + if (get_field(rd_val, DM_SBCS_SBERROR) == 0) LOG_INFO("System Bus Access Test 4: Illegal address write test PASSED."); else { LOG_ERROR("System Bus Access Test 4: Illegal address write test FAILED, unable to clear to 0."); @@ -4224,21 +4224,21 @@ static int riscv013_test_sba_config_reg(struct target *target, } /* Test 5: Write with unsupported sbaccess size */ - uint32_t sbaccess128 = get_field(sbcs_orig, DMI_SBCS_SBACCESS128); + uint32_t sbaccess128 = get_field(sbcs_orig, DM_SBCS_SBACCESS128); if (sbaccess128) { LOG_INFO("System Bus Access Test 5: SBCS sbaccess error test PASSED, all sbaccess sizes supported."); } else { - sbcs = set_field(sbcs_orig, DMI_SBCS_SBACCESS, 4); + sbcs = set_field(sbcs_orig, DM_SBCS_SBACCESS, 4); write_memory_sba_simple(target, legal_address, test_patterns, 1, sbcs); - dmi_read(target, &rd_val, DMI_SBCS); - if (get_field(rd_val, DMI_SBCS_SBERROR) == 4) { - sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 4); - dmi_write(target, DMI_SBCS, sbcs); - dmi_read(target, &rd_val, DMI_SBCS); - if (get_field(rd_val, DMI_SBCS_SBERROR) == 0) + dmi_read(target, &rd_val, DM_SBCS); + if (get_field(rd_val, DM_SBCS_SBERROR) == 4) { + sbcs = set_field(sbcs_orig, DM_SBCS_SBERROR, 4); + dmi_write(target, DM_SBCS, sbcs); + dmi_read(target, &rd_val, DM_SBCS); + if (get_field(rd_val, DM_SBCS_SBERROR) == 0) LOG_INFO("System Bus Access Test 5: SBCS sbaccess error test PASSED."); else { LOG_ERROR("System Bus Access Test 5: SBCS sbaccess error test FAILED, unable to clear to 0."); @@ -4251,16 +4251,16 @@ static int riscv013_test_sba_config_reg(struct target *target, } /* Test 6: Write to misaligned address */ - sbcs = set_field(sbcs_orig, DMI_SBCS_SBACCESS, 1); + sbcs = set_field(sbcs_orig, DM_SBCS_SBACCESS, 1); write_memory_sba_simple(target, legal_address+1, test_patterns, 1, sbcs); - dmi_read(target, &rd_val, DMI_SBCS); - if (get_field(rd_val, DMI_SBCS_SBERROR) == 3) { - sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 3); - dmi_write(target, DMI_SBCS, sbcs); - dmi_read(target, &rd_val, DMI_SBCS); - if (get_field(rd_val, DMI_SBCS_SBERROR) == 0) + dmi_read(target, &rd_val, DM_SBCS); + if (get_field(rd_val, DM_SBCS_SBERROR) == 3) { + sbcs = set_field(sbcs_orig, DM_SBCS_SBERROR, 3); + dmi_write(target, DM_SBCS, sbcs); + dmi_read(target, &rd_val, DM_SBCS); + if (get_field(rd_val, DM_SBCS_SBERROR) == 0) LOG_INFO("System Bus Access Test 6: SBCS address alignment error test PASSED"); else { LOG_ERROR("System Bus Access Test 6: SBCS address alignment error test FAILED, unable to clear to 0."); @@ -4274,21 +4274,21 @@ static int riscv013_test_sba_config_reg(struct target *target, /* Test 7: Set sbbusyerror, only run this case in simulation as it is likely * impossible to hit otherwise */ if (run_sbbusyerror_test) { - sbcs = set_field(sbcs_orig, DMI_SBCS_SBREADONADDR, 1); - dmi_write(target, DMI_SBCS, sbcs); + sbcs = set_field(sbcs_orig, DM_SBCS_SBREADONADDR, 1); + dmi_write(target, DM_SBCS, sbcs); for (int i = 0; i < 16; i++) - dmi_write(target, DMI_SBDATA0, 0xdeadbeef); + dmi_write(target, DM_SBDATA0, 0xdeadbeef); for (int i = 0; i < 16; i++) - dmi_write(target, DMI_SBADDRESS0, legal_address); - - dmi_read(target, &rd_val, DMI_SBCS); - if (get_field(rd_val, DMI_SBCS_SBBUSYERROR)) { - sbcs = set_field(sbcs_orig, DMI_SBCS_SBBUSYERROR, 1); - dmi_write(target, DMI_SBCS, sbcs); - dmi_read(target, &rd_val, DMI_SBCS); - if (get_field(rd_val, DMI_SBCS_SBBUSYERROR) == 0) + dmi_write(target, DM_SBADDRESS0, legal_address); + + dmi_read(target, &rd_val, DM_SBCS); + if (get_field(rd_val, DM_SBCS_SBBUSYERROR)) { + sbcs = set_field(sbcs_orig, DM_SBCS_SBBUSYERROR, 1); + dmi_write(target, DM_SBCS, sbcs); + dmi_read(target, &rd_val, DM_SBCS); + if (get_field(rd_val, DM_SBCS_SBBUSYERROR) == 0) LOG_INFO("System Bus Access Test 7: SBCS sbbusyerror test PASSED."); else { LOG_ERROR("System Bus Access Test 7: SBCS sbbusyerror test FAILED, unable to clear to 0."); @@ -4318,26 +4318,26 @@ void write_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t rd_sbcs; uint32_t masked_addr; - uint32_t sba_size = get_field(info->sbcs, DMI_SBCS_SBASIZE); + uint32_t sba_size = get_field(info->sbcs, DM_SBCS_SBASIZE); read_sbcs_nonbusy(target, &rd_sbcs); - uint32_t sbcs_no_readonaddr = set_field(sbcs, DMI_SBCS_SBREADONADDR, 0); - dmi_write(target, DMI_SBCS, sbcs_no_readonaddr); + uint32_t sbcs_no_readonaddr = set_field(sbcs, DM_SBCS_SBREADONADDR, 0); + dmi_write(target, DM_SBCS, sbcs_no_readonaddr); for (uint32_t i = 0; i < sba_size/32; i++) { masked_addr = (addr >> 32*i) & 0xffffffff; if (i != 3) - dmi_write(target, DMI_SBADDRESS0+i, masked_addr); + dmi_write(target, DM_SBADDRESS0+i, masked_addr); else - dmi_write(target, DMI_SBADDRESS3, masked_addr); + dmi_write(target, DM_SBADDRESS3, masked_addr); } /* Write SBDATA registers starting with highest address, since write to * SBDATA0 triggers write */ for (int i = write_size-1; i >= 0; i--) - dmi_write(target, DMI_SBDATA0+i, write_data[i]); + dmi_write(target, DM_SBDATA0+i, write_data[i]); } void read_memory_sba_simple(struct target *target, target_addr_t addr, @@ -4348,27 +4348,27 @@ void read_memory_sba_simple(struct target *target, target_addr_t addr, uint32_t rd_sbcs; uint32_t masked_addr; - uint32_t sba_size = get_field(info->sbcs, DMI_SBCS_SBASIZE); + uint32_t sba_size = get_field(info->sbcs, DM_SBCS_SBASIZE); read_sbcs_nonbusy(target, &rd_sbcs); - uint32_t sbcs_readonaddr = set_field(sbcs, DMI_SBCS_SBREADONADDR, 1); - dmi_write(target, DMI_SBCS, sbcs_readonaddr); + uint32_t sbcs_readonaddr = set_field(sbcs, DM_SBCS_SBREADONADDR, 1); + dmi_write(target, DM_SBCS, sbcs_readonaddr); /* Write addresses starting with highest address register */ for (int i = sba_size/32-1; i >= 0; i--) { masked_addr = (addr >> 32*i) & 0xffffffff; if (i != 3) - dmi_write(target, DMI_SBADDRESS0+i, masked_addr); + dmi_write(target, DM_SBADDRESS0+i, masked_addr); else - dmi_write(target, DMI_SBADDRESS3, masked_addr); + dmi_write(target, DM_SBADDRESS3, masked_addr); } read_sbcs_nonbusy(target, &rd_sbcs); for (uint32_t i = 0; i < read_size; i++) - dmi_read(target, &(rd_buf[i]), DMI_SBDATA0+i); + dmi_read(target, &(rd_buf[i]), DM_SBDATA0+i); } int riscv013_dmi_write_u64_bits(struct target *target) @@ -4413,30 +4413,30 @@ static int riscv013_step_or_resume_current_hart(struct target *target, } /* Issue the resume command, and then wait for the current hart to resume. */ - uint32_t dmcontrol = DMI_DMCONTROL_DMACTIVE | DMI_DMCONTROL_RESUMEREQ; + uint32_t dmcontrol = DM_DMCONTROL_DMACTIVE | DM_DMCONTROL_RESUMEREQ; if (use_hasel) - dmcontrol |= DMI_DMCONTROL_HASEL; + dmcontrol |= DM_DMCONTROL_HASEL; dmcontrol = set_hartsel(dmcontrol, r->current_hartid); - dmi_write(target, DMI_DMCONTROL, dmcontrol); + dmi_write(target, DM_DMCONTROL, dmcontrol); - dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_HASEL, 0); - dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_RESUMEREQ, 0); + dmcontrol = set_field(dmcontrol, DM_DMCONTROL_HASEL, 0); + dmcontrol = set_field(dmcontrol, DM_DMCONTROL_RESUMEREQ, 0); uint32_t dmstatus; for (size_t i = 0; i < 256; ++i) { usleep(10); if (dmstatus_read(target, &dmstatus, true) != ERROR_OK) return ERROR_FAIL; - if (get_field(dmstatus, DMI_DMSTATUS_ALLRESUMEACK) == 0) + if (get_field(dmstatus, DM_DMSTATUS_ALLRESUMEACK) == 0) continue; - if (step && get_field(dmstatus, DMI_DMSTATUS_ALLHALTED) == 0) + if (step && get_field(dmstatus, DM_DMSTATUS_ALLHALTED) == 0) continue; - dmi_write(target, DMI_DMCONTROL, dmcontrol); + dmi_write(target, DM_DMCONTROL, dmcontrol); return ERROR_OK; } - dmi_write(target, DMI_DMCONTROL, dmcontrol); + dmi_write(target, DM_DMCONTROL, dmcontrol); LOG_ERROR("unable to resume hart %d", r->current_hartid); if (dmstatus_read(target, &dmstatus, true) != ERROR_OK) @@ -4457,9 +4457,9 @@ void riscv013_clear_abstract_error(struct target *target) /* Wait for busy to go away. */ time_t start = time(NULL); uint32_t abstractcs; - dmi_read(target, &abstractcs, DMI_ABSTRACTCS); - while (get_field(abstractcs, DMI_ABSTRACTCS_BUSY)) { - dmi_read(target, &abstractcs, DMI_ABSTRACTCS); + dmi_read(target, &abstractcs, DM_ABSTRACTCS); + while (get_field(abstractcs, DM_ABSTRACTCS_BUSY)) { + dmi_read(target, &abstractcs, DM_ABSTRACTCS); if (time(NULL) - start > riscv_command_timeout_sec) { LOG_ERROR("abstractcs.busy is not going low after %d seconds " @@ -4471,7 +4471,7 @@ void riscv013_clear_abstract_error(struct target *target) } } /* Clear the error status. */ - dmi_write(target, DMI_ABSTRACTCS, DMI_ABSTRACTCS_CMDERR); + dmi_write(target, DM_ABSTRACTCS, DM_ABSTRACTCS_CMDERR); } #ifdef _WIN32 @@ -4531,7 +4531,7 @@ int riscv013_test_compliance(struct target *target) int total_tests = 0; int passed_tests = 0; - uint32_t dmcontrol_orig = DMI_DMCONTROL_DMACTIVE; + uint32_t dmcontrol_orig = DM_DMCONTROL_DMACTIVE; uint32_t dmcontrol; uint32_t testvar; uint32_t testvar_read; @@ -4545,17 +4545,17 @@ int riscv013_test_compliance(struct target *target) or it is tied to 0. This check doesn't really do anything, but it does attempt to set the bit to 1 and then back to 0, which needs to work if its implemented. */ - COMPLIANCE_WRITE(target, DMI_DMCONTROL, set_field(dmcontrol_orig, DMI_DMCONTROL_HARTRESET, 1)); - COMPLIANCE_WRITE(target, DMI_DMCONTROL, set_field(dmcontrol_orig, DMI_DMCONTROL_HARTRESET, 0)); - COMPLIANCE_READ(target, &dmcontrol, DMI_DMCONTROL); - COMPLIANCE_TEST((get_field(dmcontrol, DMI_DMCONTROL_HARTRESET) == 0), + COMPLIANCE_WRITE(target, DM_DMCONTROL, set_field(dmcontrol_orig, DM_DMCONTROL_HARTRESET, 1)); + COMPLIANCE_WRITE(target, DM_DMCONTROL, set_field(dmcontrol_orig, DM_DMCONTROL_HARTRESET, 0)); + COMPLIANCE_READ(target, &dmcontrol, DM_DMCONTROL); + COMPLIANCE_TEST((get_field(dmcontrol, DM_DMCONTROL_HARTRESET) == 0), "DMCONTROL.hartreset can be 0 or RW."); /* hasel */ - COMPLIANCE_WRITE(target, DMI_DMCONTROL, set_field(dmcontrol_orig, DMI_DMCONTROL_HASEL, 1)); - COMPLIANCE_WRITE(target, DMI_DMCONTROL, set_field(dmcontrol_orig, DMI_DMCONTROL_HASEL, 0)); - COMPLIANCE_READ(target, &dmcontrol, DMI_DMCONTROL); - COMPLIANCE_TEST((get_field(dmcontrol, DMI_DMCONTROL_HASEL) == 0), + COMPLIANCE_WRITE(target, DM_DMCONTROL, set_field(dmcontrol_orig, DM_DMCONTROL_HASEL, 1)); + COMPLIANCE_WRITE(target, DM_DMCONTROL, set_field(dmcontrol_orig, DM_DMCONTROL_HASEL, 0)); + COMPLIANCE_READ(target, &dmcontrol, DM_DMCONTROL); + COMPLIANCE_TEST((get_field(dmcontrol, DM_DMCONTROL_HASEL) == 0), "DMCONTROL.hasel can be 0 or RW."); /* TODO: test that hamask registers exist if hasel does. */ @@ -4564,7 +4564,7 @@ int riscv013_test_compliance(struct target *target) /* This bit is not actually readable according to the spec, so nothing to check.*/ /* DMSTATUS */ - COMPLIANCE_CHECK_RO(target, DMI_DMSTATUS); + COMPLIANCE_CHECK_RO(target, DM_DMSTATUS); /* resumereq */ /* This bit is not actually readable according to the spec, so nothing to check.*/ @@ -4575,14 +4575,14 @@ int riscv013_test_compliance(struct target *target) /* HARTINFO: Read-Only. This is per-hart, so need to adjust hartsel. */ uint32_t hartinfo; - COMPLIANCE_READ(target, &hartinfo, DMI_HARTINFO); + COMPLIANCE_READ(target, &hartinfo, DM_HARTINFO); for (int hartsel = 0; hartsel < riscv_count_harts(target); hartsel++) { COMPLIANCE_MUST_PASS(riscv_set_current_hartid(target, hartsel)); - COMPLIANCE_CHECK_RO(target, DMI_HARTINFO); + COMPLIANCE_CHECK_RO(target, DM_HARTINFO); /* $dscratch CSRs */ - uint32_t nscratch = get_field(hartinfo, DMI_HARTINFO_NSCRATCH); + uint32_t nscratch = get_field(hartinfo, DM_HARTINFO_NSCRATCH); for (unsigned int d = 0; d < nscratch; d++) { riscv_reg_t testval, testval_read; /* Because DSCRATCH is not guaranteed to last across PB executions, need to put @@ -4614,7 +4614,7 @@ int riscv013_test_compliance(struct target *target) } } /* TODO: dataaccess */ - if (get_field(hartinfo, DMI_HARTINFO_DATAACCESS)) { + if (get_field(hartinfo, DM_HARTINFO_DATAACCESS)) { /* TODO: Shadowed in memory map. */ /* TODO: datasize */ /* TODO: dataaddr */ @@ -4633,16 +4633,16 @@ int riscv013_test_compliance(struct target *target) for (int i = 0; i < MIN(riscv_count_harts(target), 32); i++) expected_haltsum0 |= (1 << i); - COMPLIANCE_READ(target, &testvar_read, DMI_HALTSUM0); + COMPLIANCE_READ(target, &testvar_read, DM_HALTSUM0); COMPLIANCE_TEST(testvar_read == expected_haltsum0, "HALTSUM0 should report summary of up to 32 halted harts"); - COMPLIANCE_WRITE(target, DMI_HALTSUM0, 0xffffffff); - COMPLIANCE_READ(target, &testvar_read, DMI_HALTSUM0); + COMPLIANCE_WRITE(target, DM_HALTSUM0, 0xffffffff); + COMPLIANCE_READ(target, &testvar_read, DM_HALTSUM0); COMPLIANCE_TEST(testvar_read == expected_haltsum0, "HALTSUM0 should be R/O"); - COMPLIANCE_WRITE(target, DMI_HALTSUM0, 0x0); - COMPLIANCE_READ(target, &testvar_read, DMI_HALTSUM0); + COMPLIANCE_WRITE(target, DM_HALTSUM0, 0x0); + COMPLIANCE_READ(target, &testvar_read, DM_HALTSUM0); COMPLIANCE_TEST(testvar_read == expected_haltsum0, "HALTSUM0 should be R/O"); /* HALTSUM1 */ @@ -4650,16 +4650,16 @@ int riscv013_test_compliance(struct target *target) for (int i = 0; i < MIN(riscv_count_harts(target), 1024); i += 32) expected_haltsum1 |= (1 << (i/32)); - COMPLIANCE_READ(target, &testvar_read, DMI_HALTSUM1); + COMPLIANCE_READ(target, &testvar_read, DM_HALTSUM1); COMPLIANCE_TEST(testvar_read == expected_haltsum1, "HALTSUM1 should report summary of up to 1024 halted harts"); - COMPLIANCE_WRITE(target, DMI_HALTSUM1, 0xffffffff); - COMPLIANCE_READ(target, &testvar_read, DMI_HALTSUM1); + COMPLIANCE_WRITE(target, DM_HALTSUM1, 0xffffffff); + COMPLIANCE_READ(target, &testvar_read, DM_HALTSUM1); COMPLIANCE_TEST(testvar_read == expected_haltsum1, "HALTSUM1 should be R/O"); - COMPLIANCE_WRITE(target, DMI_HALTSUM1, 0x0); - COMPLIANCE_READ(target, &testvar_read, DMI_HALTSUM1); + COMPLIANCE_WRITE(target, DM_HALTSUM1, 0x0); + COMPLIANCE_READ(target, &testvar_read, DM_HALTSUM1); COMPLIANCE_TEST(testvar_read == expected_haltsum1, "HALTSUM1 should be R/O"); /* TODO: HAWINDOWSEL */ @@ -4669,38 +4669,38 @@ int riscv013_test_compliance(struct target *target) /* ABSTRACTCS */ uint32_t abstractcs; - COMPLIANCE_READ(target, &abstractcs, DMI_ABSTRACTCS); + COMPLIANCE_READ(target, &abstractcs, DM_ABSTRACTCS); /* Check that all reported Data Words are really R/W */ for (int invert = 0; invert < 2; invert++) { - for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_DATACOUNT); i++) { + for (unsigned int i = 0; i < get_field(abstractcs, DM_ABSTRACTCS_DATACOUNT); i++) { testvar = (i + 1) * 0x11111111; if (invert) testvar = ~testvar; - COMPLIANCE_WRITE(target, DMI_DATA0 + i, testvar); + COMPLIANCE_WRITE(target, DM_DATA0 + i, testvar); } - for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_DATACOUNT); i++) { + for (unsigned int i = 0; i < get_field(abstractcs, DM_ABSTRACTCS_DATACOUNT); i++) { testvar = (i + 1) * 0x11111111; if (invert) testvar = ~testvar; - COMPLIANCE_READ(target, &testvar_read, DMI_DATA0 + i); + COMPLIANCE_READ(target, &testvar_read, DM_DATA0 + i); COMPLIANCE_TEST(testvar_read == testvar, "All reported DATA words must be R/W"); } } /* Check that all reported ProgBuf words are really R/W */ for (int invert = 0; invert < 2; invert++) { - for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_PROGBUFSIZE); i++) { + for (unsigned int i = 0; i < get_field(abstractcs, DM_ABSTRACTCS_PROGBUFSIZE); i++) { testvar = (i + 1) * 0x11111111; if (invert) testvar = ~testvar; - COMPLIANCE_WRITE(target, DMI_PROGBUF0 + i, testvar); + COMPLIANCE_WRITE(target, DM_PROGBUF0 + i, testvar); } - for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_PROGBUFSIZE); i++) { + for (unsigned int i = 0; i < get_field(abstractcs, DM_ABSTRACTCS_PROGBUFSIZE); i++) { testvar = (i + 1) * 0x11111111; if (invert) testvar = ~testvar; - COMPLIANCE_READ(target, &testvar_read, DMI_PROGBUF0 + i); + COMPLIANCE_READ(target, &testvar_read, DM_PROGBUF0 + i); COMPLIANCE_TEST(testvar_read == testvar, "All reported PROGBUF words must be R/W"); } } @@ -4710,17 +4710,17 @@ int riscv013_test_compliance(struct target *target) /* COMMAND According to the spec, this register is only W, so can't really check the read result. But at any rate, this is not legal and should cause an error. */ - COMPLIANCE_WRITE(target, DMI_COMMAND, 0xAAAAAAAA); - COMPLIANCE_READ(target, &testvar_read, DMI_ABSTRACTCS); - COMPLIANCE_TEST(get_field(testvar_read, DMI_ABSTRACTCS_CMDERR) == CMDERR_NOT_SUPPORTED, + COMPLIANCE_WRITE(target, DM_COMMAND, 0xAAAAAAAA); + COMPLIANCE_READ(target, &testvar_read, DM_ABSTRACTCS); + COMPLIANCE_TEST(get_field(testvar_read, DM_ABSTRACTCS_CMDERR) == CMDERR_NOT_SUPPORTED, "Illegal COMMAND should result in UNSUPPORTED"); - COMPLIANCE_WRITE(target, DMI_ABSTRACTCS, DMI_ABSTRACTCS_CMDERR); + COMPLIANCE_WRITE(target, DM_ABSTRACTCS, DM_ABSTRACTCS_CMDERR); - COMPLIANCE_WRITE(target, DMI_COMMAND, 0x55555555); - COMPLIANCE_READ(target, &testvar_read, DMI_ABSTRACTCS); - COMPLIANCE_TEST(get_field(testvar_read, DMI_ABSTRACTCS_CMDERR) == CMDERR_NOT_SUPPORTED, + COMPLIANCE_WRITE(target, DM_COMMAND, 0x55555555); + COMPLIANCE_READ(target, &testvar_read, DM_ABSTRACTCS); + COMPLIANCE_TEST(get_field(testvar_read, DM_ABSTRACTCS_CMDERR) == CMDERR_NOT_SUPPORTED, "Illegal COMMAND should result in UNSUPPORTED"); - COMPLIANCE_WRITE(target, DMI_ABSTRACTCS, DMI_ABSTRACTCS_CMDERR); + COMPLIANCE_WRITE(target, DM_ABSTRACTCS, DM_ABSTRACTCS_CMDERR); /* Basic Abstract Commands */ for (unsigned int i = 1; i < 32; i = i << 1) { @@ -4742,11 +4742,11 @@ int riscv013_test_compliance(struct target *target) /* ABSTRACTAUTO See which bits are actually writable */ - COMPLIANCE_WRITE(target, DMI_ABSTRACTAUTO, 0xFFFFFFFF); + COMPLIANCE_WRITE(target, DM_ABSTRACTAUTO, 0xFFFFFFFF); uint32_t abstractauto; uint32_t busy; - COMPLIANCE_READ(target, &abstractauto, DMI_ABSTRACTAUTO); - COMPLIANCE_WRITE(target, DMI_ABSTRACTAUTO, 0x0); + COMPLIANCE_READ(target, &abstractauto, DM_ABSTRACTAUTO); + COMPLIANCE_WRITE(target, DM_ABSTRACTAUTO, 0x0); if (abstractauto > 0) { /* This mechanism only works when you have a reasonable sized progbuf, which is not a true compliance requirement. */ @@ -4761,39 +4761,39 @@ int riscv013_test_compliance(struct target *target) COMPLIANCE_MUST_PASS(riscv_program_insert(&program, wfi())); COMPLIANCE_MUST_PASS(riscv_program_addi(&program, GDB_REGNO_S0, GDB_REGNO_S0, 1)); COMPLIANCE_MUST_PASS(riscv_program_ebreak(&program)); - COMPLIANCE_WRITE(target, DMI_ABSTRACTAUTO, 0x0); + COMPLIANCE_WRITE(target, DM_ABSTRACTAUTO, 0x0); COMPLIANCE_MUST_PASS(riscv_program_exec(&program, target)); testvar++; - COMPLIANCE_WRITE(target, DMI_ABSTRACTAUTO, 0xFFFFFFFF); - COMPLIANCE_READ(target, &abstractauto, DMI_ABSTRACTAUTO); - uint32_t autoexec_data = get_field(abstractauto, DMI_ABSTRACTAUTO_AUTOEXECDATA); - uint32_t autoexec_progbuf = get_field(abstractauto, DMI_ABSTRACTAUTO_AUTOEXECPROGBUF); + COMPLIANCE_WRITE(target, DM_ABSTRACTAUTO, 0xFFFFFFFF); + COMPLIANCE_READ(target, &abstractauto, DM_ABSTRACTAUTO); + uint32_t autoexec_data = get_field(abstractauto, DM_ABSTRACTAUTO_AUTOEXECDATA); + uint32_t autoexec_progbuf = get_field(abstractauto, DM_ABSTRACTAUTO_AUTOEXECPROGBUF); for (unsigned int i = 0; i < 12; i++) { - COMPLIANCE_READ(target, &testvar_read, DMI_DATA0 + i); + COMPLIANCE_READ(target, &testvar_read, DM_DATA0 + i); do { - COMPLIANCE_READ(target, &testvar_read, DMI_ABSTRACTCS); - busy = get_field(testvar_read, DMI_ABSTRACTCS_BUSY); + COMPLIANCE_READ(target, &testvar_read, DM_ABSTRACTCS); + busy = get_field(testvar_read, DM_ABSTRACTCS_BUSY); } while (busy); if (autoexec_data & (1 << i)) { - COMPLIANCE_TEST(i < get_field(abstractcs, DMI_ABSTRACTCS_DATACOUNT), + COMPLIANCE_TEST(i < get_field(abstractcs, DM_ABSTRACTCS_DATACOUNT), "AUTOEXEC may be writable up to DATACOUNT bits."); testvar++; } } for (unsigned int i = 0; i < 16; i++) { - COMPLIANCE_READ(target, &testvar_read, DMI_PROGBUF0 + i); + COMPLIANCE_READ(target, &testvar_read, DM_PROGBUF0 + i); do { - COMPLIANCE_READ(target, &testvar_read, DMI_ABSTRACTCS); - busy = get_field(testvar_read, DMI_ABSTRACTCS_BUSY); + COMPLIANCE_READ(target, &testvar_read, DM_ABSTRACTCS); + busy = get_field(testvar_read, DM_ABSTRACTCS_BUSY); } while (busy); if (autoexec_progbuf & (1 << i)) { - COMPLIANCE_TEST(i < get_field(abstractcs, DMI_ABSTRACTCS_PROGBUFSIZE), + COMPLIANCE_TEST(i < get_field(abstractcs, DM_ABSTRACTCS_PROGBUFSIZE), "AUTOEXEC may be writable up to PROGBUFSIZE bits."); testvar++; } } - COMPLIANCE_WRITE(target, DMI_ABSTRACTAUTO, 0); + COMPLIANCE_WRITE(target, DM_ABSTRACTAUTO, 0); COMPLIANCE_TEST(ERROR_OK == register_read_direct(target, &value, GDB_REGNO_S0), "Need to be able to read S0 to test ABSTRACTAUTO"); @@ -4852,20 +4852,20 @@ int riscv013_test_compliance(struct target *target) */ /* Write some registers. They should not be impacted by ndmreset. */ - COMPLIANCE_WRITE(target, DMI_COMMAND, 0xFFFFFFFF); + COMPLIANCE_WRITE(target, DM_COMMAND, 0xFFFFFFFF); - for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_PROGBUFSIZE); i++) { + for (unsigned int i = 0; i < get_field(abstractcs, DM_ABSTRACTCS_PROGBUFSIZE); i++) { testvar = (i + 1) * 0x11111111; - COMPLIANCE_WRITE(target, DMI_PROGBUF0 + i, testvar); + COMPLIANCE_WRITE(target, DM_PROGBUF0 + i, testvar); } - for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_DATACOUNT); i++) { + for (unsigned int i = 0; i < get_field(abstractcs, DM_ABSTRACTCS_DATACOUNT); i++) { testvar = (i + 1) * 0x11111111; - COMPLIANCE_WRITE(target, DMI_DATA0 + i, testvar); + COMPLIANCE_WRITE(target, DM_DATA0 + i, testvar); } - COMPLIANCE_WRITE(target, DMI_ABSTRACTAUTO, 0xFFFFFFFF); - COMPLIANCE_READ(target, &abstractauto, DMI_ABSTRACTAUTO); + COMPLIANCE_WRITE(target, DM_ABSTRACTAUTO, 0xFFFFFFFF); + COMPLIANCE_READ(target, &abstractauto, DM_ABSTRACTAUTO); /* Pulse reset. */ target->reset_halt = true; @@ -4874,25 +4874,25 @@ int riscv013_test_compliance(struct target *target) COMPLIANCE_TEST(ERROR_OK == deassert_reset(target), "Must be able to deassert NDMRESET"); /* Verify that most stuff is not affected by ndmreset. */ - COMPLIANCE_READ(target, &testvar_read, DMI_ABSTRACTCS); - COMPLIANCE_TEST(get_field(testvar_read, DMI_ABSTRACTCS_CMDERR) == CMDERR_NOT_SUPPORTED, - "NDMRESET should not affect DMI_ABSTRACTCS"); - COMPLIANCE_READ(target, &testvar_read, DMI_ABSTRACTAUTO); - COMPLIANCE_TEST(testvar_read == abstractauto, "NDMRESET should not affect DMI_ABSTRACTAUTO"); + COMPLIANCE_READ(target, &testvar_read, DM_ABSTRACTCS); + COMPLIANCE_TEST(get_field(testvar_read, DM_ABSTRACTCS_CMDERR) == CMDERR_NOT_SUPPORTED, + "NDMRESET should not affect DM_ABSTRACTCS"); + COMPLIANCE_READ(target, &testvar_read, DM_ABSTRACTAUTO); + COMPLIANCE_TEST(testvar_read == abstractauto, "NDMRESET should not affect DM_ABSTRACTAUTO"); /* Clean up to avoid future test failures */ - COMPLIANCE_WRITE(target, DMI_ABSTRACTCS, DMI_ABSTRACTCS_CMDERR); - COMPLIANCE_WRITE(target, DMI_ABSTRACTAUTO, 0); + COMPLIANCE_WRITE(target, DM_ABSTRACTCS, DM_ABSTRACTCS_CMDERR); + COMPLIANCE_WRITE(target, DM_ABSTRACTAUTO, 0); - for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_PROGBUFSIZE); i++) { + for (unsigned int i = 0; i < get_field(abstractcs, DM_ABSTRACTCS_PROGBUFSIZE); i++) { testvar = (i + 1) * 0x11111111; - COMPLIANCE_READ(target, &testvar_read, DMI_PROGBUF0 + i); + COMPLIANCE_READ(target, &testvar_read, DM_PROGBUF0 + i); COMPLIANCE_TEST(testvar_read == testvar, "PROGBUF words must not be affected by NDMRESET"); } - for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_DATACOUNT); i++) { + for (unsigned int i = 0; i < get_field(abstractcs, DM_ABSTRACTCS_DATACOUNT); i++) { testvar = (i + 1) * 0x11111111; - COMPLIANCE_READ(target, &testvar_read, DMI_DATA0 + i); + COMPLIANCE_READ(target, &testvar_read, DM_DATA0 + i); COMPLIANCE_TEST(testvar_read == testvar, "DATA words must not be affected by NDMRESET"); } @@ -4909,20 +4909,20 @@ int riscv013_test_compliance(struct target *target) /* DMACTIVE -- deasserting DMACTIVE should reset all the above values. */ /* Toggle dmactive */ - COMPLIANCE_WRITE(target, DMI_DMCONTROL, 0); - COMPLIANCE_WRITE(target, DMI_DMCONTROL, DMI_DMCONTROL_DMACTIVE); - COMPLIANCE_READ(target, &testvar_read, DMI_ABSTRACTCS); - COMPLIANCE_TEST(get_field(testvar_read, DMI_ABSTRACTCS_CMDERR) == 0, "ABSTRACTCS.cmderr should reset to 0"); - COMPLIANCE_READ(target, &testvar_read, DMI_ABSTRACTAUTO); + COMPLIANCE_WRITE(target, DM_DMCONTROL, 0); + COMPLIANCE_WRITE(target, DM_DMCONTROL, DM_DMCONTROL_DMACTIVE); + COMPLIANCE_READ(target, &testvar_read, DM_ABSTRACTCS); + COMPLIANCE_TEST(get_field(testvar_read, DM_ABSTRACTCS_CMDERR) == 0, "ABSTRACTCS.cmderr should reset to 0"); + COMPLIANCE_READ(target, &testvar_read, DM_ABSTRACTAUTO); COMPLIANCE_TEST(testvar_read == 0, "ABSTRACTAUTO should reset to 0"); - for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_PROGBUFSIZE); i++) { - COMPLIANCE_READ(target, &testvar_read, DMI_PROGBUF0 + i); + for (unsigned int i = 0; i < get_field(abstractcs, DM_ABSTRACTCS_PROGBUFSIZE); i++) { + COMPLIANCE_READ(target, &testvar_read, DM_PROGBUF0 + i); COMPLIANCE_TEST(testvar_read == 0, "PROGBUF words should reset to 0"); } - for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_DATACOUNT); i++) { - COMPLIANCE_READ(target, &testvar_read, DMI_DATA0 + i); + for (unsigned int i = 0; i < get_field(abstractcs, DM_ABSTRACTCS_DATACOUNT); i++) { + COMPLIANCE_READ(target, &testvar_read, DM_DATA0 + i); COMPLIANCE_TEST(testvar_read == 0, "DATA words should reset to 0"); } |