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author | Tim Newsome <tim@sifive.com> | 2022-04-27 13:02:00 -0700 |
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committer | Tim Newsome <tim@sifive.com> | 2022-04-30 09:59:46 -0700 |
commit | 1979ad5594ba1ebf1f5e0876f780c4c1c8f187cb (patch) | |
tree | 258a0f4dbb023b8ef834cd8d05697fcaefde97f5 | |
parent | 73199226dfaf2df1c009509358c3a48fc3b0970d (diff) | |
download | riscv-openocd-1979ad5594ba1ebf1f5e0876f780c4c1c8f187cb.zip riscv-openocd-1979ad5594ba1ebf1f5e0876f780c4c1c8f187cb.tar.gz riscv-openocd-1979ad5594ba1ebf1f5e0876f780c4c1c8f187cb.tar.bz2 |
If we know which trigger hit, don't disassemble.
Change-Id: I1d7b6ffa91b0557e2e74e544e4b35033ed3e3553
Signed-off-by: Tim Newsome <tim@sifive.com>
-rw-r--r-- | src/target/riscv/riscv.c | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 26824a9..4ab6d99 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -1086,12 +1086,19 @@ static int riscv_hit_trigger_hit_bit(struct target *target, uint32_t *unique_id) * and new value. */ int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint) { + RISCV_INFO(r); + LOG_DEBUG("Current hartid = %d", riscv_current_hartid(target)); - /*TODO instead of disassembling the instruction that we think caused the - * trigger, check the hit bit of each watchpoint first. The hit bit is - * simpler and more reliable to check but as it is optional and relatively - * new, not all hardware will implement it */ + /* If we identified which trigger caused the halt earlier, then just use + * that. */ + for (struct watchpoint *wp = target->watchpoints; wp; wp = wp->next) { + if (wp->unique_id == r->trigger_hit) { + *hit_watchpoint = wp; + return ERROR_OK; + } + } + riscv_reg_t dpc; riscv_get_register(target, &dpc, GDB_REGNO_DPC); const uint8_t length = 4; |