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| author | Tim Newsome <tim@sifive.com> | 2022-09-27 10:00:24 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-09-27 10:00:24 -0700 |
| commit | d427e136d3aeeb7972962d55fc4a2dffde4c24ca (patch) | |
| tree | bc304dca5fb18dd4c77136291eda2407a0ea5962 | |
| parent | 8bb25e007972a153653d3437e63bb50eb8e916e2 (diff) | |
| parent | 137141249b33cf1b2a471b959e07173ee8238fa1 (diff) | |
| download | riscv-openocd-d427e136d3aeeb7972962d55fc4a2dffde4c24ca.zip riscv-openocd-d427e136d3aeeb7972962d55fc4a2dffde4c24ca.tar.gz riscv-openocd-d427e136d3aeeb7972962d55fc4a2dffde4c24ca.tar.bz2 | |
Merge pull request #732 from en-sc/en-sc/error-code-regwrite-direct
Propagate error code in register_read/write_direct
| -rw-r--r-- | src/target/riscv/riscv-013.c | 37 |
1 files changed, 25 insertions, 12 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index a2d887e..9c12489 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1323,7 +1323,9 @@ static int register_write_direct(struct target *target, unsigned number, /* There are no instructions to move all the bits from a register, so * we need to use some scratch RAM. */ use_scratch = true; - riscv_program_insert(&program, fld(number - GDB_REGNO_FPR0, S0, 0)); + if (riscv_program_insert(&program, fld(number - GDB_REGNO_FPR0, S0, 0)) + != ERROR_OK) + return ERROR_FAIL; if (scratch_reserve(target, &scratch, &program, 8) != ERROR_OK) return ERROR_FAIL; @@ -1341,10 +1343,15 @@ static int register_write_direct(struct target *target, unsigned number, } else { if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) { - if (riscv_supports_extension(target, 'D')) - riscv_program_insert(&program, fmv_d_x(number - GDB_REGNO_FPR0, S0)); - else - riscv_program_insert(&program, fmv_w_x(number - GDB_REGNO_FPR0, S0)); + if (riscv_supports_extension(target, 'D')) { + if (riscv_program_insert(&program, + fmv_d_x(number - GDB_REGNO_FPR0, S0) != ERROR_OK)) + return ERROR_FAIL; + } else { + if (riscv_program_insert(&program, + fmv_w_x(number - GDB_REGNO_FPR0, S0) != ERROR_OK)) + return ERROR_FAIL; + } } else if (number == GDB_REGNO_VTYPE) { if (riscv_save_register(target, GDB_REGNO_S1) != ERROR_OK) return ERROR_FAIL; @@ -1363,7 +1370,8 @@ static int register_write_direct(struct target *target, unsigned number, if (riscv_program_insert(&program, vsetvl(ZERO, S0, S1)) != ERROR_OK) return ERROR_FAIL; } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) { - riscv_program_csrw(&program, S0, number); + if (riscv_program_csrw(&program, S0, number) != ERROR_OK) + return ERROR_FAIL; } else { LOG_ERROR("Unsupported register (enum gdb_regno)(%d)", number); return ERROR_FAIL; @@ -1417,9 +1425,9 @@ static int register_read_direct(struct target *target, uint64_t *value, uint32_t && riscv_xlen(target) < 64) { /* There are no instructions to move all the bits from a * register, so we need to use some scratch RAM. */ - riscv_program_insert(&program, fsd(number - GDB_REGNO_FPR0, S0, - 0)); - + if (riscv_program_insert(&program, + fsd(number - GDB_REGNO_FPR0, S0, 0)) != ERROR_OK) + return ERROR_FAIL; if (scratch_reserve(target, &scratch, &program, 8) != ERROR_OK) return ERROR_FAIL; use_scratch = true; @@ -1430,12 +1438,17 @@ static int register_read_direct(struct target *target, uint64_t *value, uint32_t return ERROR_FAIL; } } else if (riscv_supports_extension(target, 'D')) { - riscv_program_insert(&program, fmv_x_d(S0, number - GDB_REGNO_FPR0)); + if (riscv_program_insert(&program, fmv_x_d(S0, number - GDB_REGNO_FPR0)) != + ERROR_OK) + return ERROR_FAIL; } else { - riscv_program_insert(&program, fmv_x_w(S0, number - GDB_REGNO_FPR0)); + if (riscv_program_insert(&program, fmv_x_w(S0, number - GDB_REGNO_FPR0)) != + ERROR_OK) + return ERROR_FAIL; } } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) { - riscv_program_csrr(&program, S0, number); + if (riscv_program_csrr(&program, S0, number) != ERROR_OK) + return ERROR_FAIL; } else { LOG_ERROR("Unsupported register: %s", gdb_regno_name(number)); return ERROR_FAIL; |