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| author | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2018-04-27 19:59:56 +0200 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2018-05-08 15:21:49 -0700 |
| commit | da7113e02d51e869bde1233a003fdf57a8d0cc50 (patch) | |
| tree | b3f4804a5e8133b879531d3289e559d5ce3f9759 | |
| parent | 6020301640e9c77c283675fc42d967185c940521 (diff) | |
| download | riscv-openocd-da7113e02d51e869bde1233a003fdf57a8d0cc50.zip riscv-openocd-da7113e02d51e869bde1233a003fdf57a8d0cc50.tar.gz riscv-openocd-da7113e02d51e869bde1233a003fdf57a8d0cc50.tar.bz2 | |
arm_dpm: flush both scratch registers (R0 and R1)
Neither the initial loop to clear dirty registers (which visits all
registers starting at R2 and counting upwards) nor the final explicit
flushes ensure a write-back in arm_dpm_write_dirty_registers.
This change makes sure that both our scratch registers (i.e. R0 and
R1) are written back to the target.
Change-Id: If65be4f371cd40af9a0cfa97f3730b070b92e981
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-on: http://openocd.zylin.com/4506
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
| -rw-r--r-- | src/target/arm_dpm.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c index 6579099..f9b30c1 100644 --- a/src/target/arm_dpm.c +++ b/src/target/arm_dpm.c @@ -587,11 +587,13 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp) goto done; arm->pc->dirty = false; - /* flush R0 -- it's *very* dirty by now */ - retval = dpm_write_reg(dpm, &cache->reg_list[0], 0); - if (retval != ERROR_OK) - goto done; - cache->reg_list[0].dirty = false; + /* flush R0 and R1 (our scratch registers) */ + for (unsigned i = 0; i < 2; i++) { + retval = dpm_write_reg(dpm, &cache->reg_list[i], i); + if (retval != ERROR_OK) + goto done; + cache->reg_list[i].dirty = false; + } /* (void) */ dpm->finish(dpm); done: |