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| author | Tim Newsome <tim@sifive.com> | 2018-10-18 13:26:03 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-10-18 13:26:03 -0700 |
| commit | 60c37e1679615428577fe1b0b785327e1d48b4fa (patch) | |
| tree | 44023c9e983b16ffe3772e017c9736eae2a45702 | |
| parent | b986d29bc9a9b561b7a186c7c25b9243e0e46f2d (diff) | |
| download | riscv-openocd-60c37e1679615428577fe1b0b785327e1d48b4fa.zip riscv-openocd-60c37e1679615428577fe1b0b785327e1d48b4fa.tar.gz riscv-openocd-60c37e1679615428577fe1b0b785327e1d48b4fa.tar.bz2 | |
dmi_scan() allocate bytes depending on abits value (#307)
* dmi_scan() allocate bytes depending on abits value
Fixes #303.
Change-Id: Iac45959cf342180c60cd0b5462f864ad81beddd2
* Incorporate review feedback.
Change-Id: I1cc7d20fed6f2d891bec0e858fca53ece450720c
| -rw-r--r-- | src/target/riscv/riscv-013.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 34ec3c6..11a7c3c 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -458,14 +458,18 @@ static dmi_status_t dmi_scan(struct target *target, uint32_t *address_in, bool exec) { riscv013_info_t *info = get_info(target); - uint8_t in[8] = {0}; - uint8_t out[8]; + unsigned num_bits = info->abits + DTM_DMI_OP_LENGTH + DTM_DMI_DATA_LENGTH; + size_t num_bytes = (num_bits + 7) / 8; + uint8_t in[num_bytes]; + uint8_t out[num_bytes]; struct scan_field field = { - .num_bits = info->abits + DTM_DMI_OP_LENGTH + DTM_DMI_DATA_LENGTH, + .num_bits = num_bits, .out_value = out, .in_value = in }; + memset(in, 0, num_bytes); + assert(info->abits != 0); buf_set_u32(out, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, op); |