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author | Tim Newsome <tim@sifive.com> | 2018-01-30 12:30:39 -0800 |
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committer | Tim Newsome <tim@sifive.com> | 2018-01-30 12:30:39 -0800 |
commit | 6f0d70f5c82e6bd2d441fc8b982f8a4578d179a4 (patch) | |
tree | 535eae9fb24fa4c52e5af912b06357b872798332 | |
parent | ec543bdc7b834ff089bc03399f657aaeaf61de42 (diff) | |
download | riscv-openocd-6f0d70f5c82e6bd2d441fc8b982f8a4578d179a4.zip riscv-openocd-6f0d70f5c82e6bd2d441fc8b982f8a4578d179a4.tar.gz riscv-openocd-6f0d70f5c82e6bd2d441fc8b982f8a4578d179a4.tar.bz2 |
Mention register name instead of number in error
Change-Id: I5be5e57418e672fc76383fc24635cdbfb1e65578
-rw-r--r-- | src/target/riscv/riscv-013.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 730d76f..760adb3 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1913,7 +1913,7 @@ static int riscv013_get_register(struct target *target, } else { result = register_read_direct(target, value, rid); if (result != ERROR_OK) { - LOG_ERROR("Unable to read register %d", rid); + LOG_ERROR("Unable to read %s", gdb_regno_name(rid)); *value = -1; } } |