diff options
| author | Tim Newsome <tim@sifive.com> | 2017-07-06 13:41:47 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-07-06 13:41:47 -0700 |
| commit | 31e5b53a468d8111b7d3dcdf96f2505e52ac3e84 (patch) | |
| tree | 1cced1015d1204e274f5e8734061791547431857 | |
| parent | 9f1738ae49bdecf4682fcc30a034e3edaa634705 (diff) | |
| parent | 450307b66f42f402113c50aefa0fe950ed20cf7d (diff) | |
| download | riscv-openocd-31e5b53a468d8111b7d3dcdf96f2505e52ac3e84.zip riscv-openocd-31e5b53a468d8111b7d3dcdf96f2505e52ac3e84.tar.gz riscv-openocd-31e5b53a468d8111b7d3dcdf96f2505e52ac3e84.tar.bz2 | |
Merge pull request #74 from riscv/build32
Fix 32-bit build errors.
| -rw-r--r-- | src/target/riscv/batch.c | 4 | ||||
| -rw-r--r-- | src/target/riscv/riscv-013.c | 11 | ||||
| -rw-r--r-- | src/target/riscv/riscv.c | 2 |
3 files changed, 10 insertions, 7 deletions
diff --git a/src/target/riscv/batch.c b/src/target/riscv/batch.c index 5d680d5..cb5a108 100644 --- a/src/target/riscv/batch.c +++ b/src/target/riscv/batch.c @@ -94,7 +94,9 @@ size_t riscv_batch_add_dmi_read(struct riscv_batch *batch, unsigned address) riscv_batch_add_nop(batch); batch->read_keys[batch->read_keys_used] = batch->used_scans - 1; - LOG_DEBUG("read key %ld for batch 0x%p is %ld (0x%p)", batch->read_keys_used, batch, batch->used_scans - 1, (uint64_t*)batch->data_in + (batch->used_scans + 1)); + LOG_DEBUG("read key %u for batch 0x%p is %u (0x%p)", + (unsigned) batch->read_keys_used, batch, (unsigned) (batch->used_scans - 1), + (uint64_t*)batch->data_in + (batch->used_scans + 1)); return batch->read_keys_used++; } diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 509f39e..96187f2 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1642,9 +1642,10 @@ static int write_memory(struct target *target, target_addr_t address, * the data was all copied. */ riscv_addr_t cur_addr = 0xbadbeef; riscv_addr_t fin_addr = address + (count * size); - LOG_DEBUG("writing until final address 0x%016lx", fin_addr); + LOG_DEBUG("writing until final address 0x%016" PRIx64, fin_addr); while ((cur_addr = riscv_read_debug_buffer_x(target, d_addr)) < fin_addr) { - LOG_DEBUG("transferring burst starting at address 0x%016lx", cur_addr); + LOG_DEBUG("transferring burst starting at address 0x%016" PRIx64, + cur_addr); riscv_addr_t start = (cur_addr - address) / size; assert (cur_addr > address); struct riscv_batch *batch = riscv_batch_alloc( @@ -1769,7 +1770,7 @@ static riscv_reg_t riscv013_get_register(struct target *target, int hid, int rid register_read_direct(target, &out, rid); } else if (rid == GDB_REGNO_PC) { register_read_direct(target, &out, GDB_REGNO_DPC); - LOG_DEBUG("read PC from DPC: 0x%016lx", out); + LOG_DEBUG("read PC from DPC: 0x%016" PRIx64, out); } else if (rid == GDB_REGNO_PRIV) { uint64_t dcsr; register_read_direct(target, &dcsr, CSR_DCSR); @@ -1797,11 +1798,11 @@ static void riscv013_set_register(struct target *target, int hid, int rid, uint6 if (rid <= GDB_REGNO_XPR31) { register_write_direct(target, rid, value); } else if (rid == GDB_REGNO_PC) { - LOG_DEBUG("writing PC to DPC: 0x%016lx", value); + LOG_DEBUG("writing PC to DPC: 0x%016" PRIx64, value); register_write_direct(target, GDB_REGNO_DPC, value); uint64_t actual_value; register_read_direct(target, &actual_value, GDB_REGNO_DPC); - LOG_DEBUG(" actual DPC written: 0x%016lx", actual_value); + LOG_DEBUG(" actual DPC written: 0x%016" PRIx64, actual_value); assert(value == actual_value); } else if (rid == GDB_REGNO_PRIV) { uint64_t dcsr; diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 377ab78..4fe027b 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -1031,7 +1031,7 @@ void riscv_set_current_hartid(struct target *target, int hartid) /* Avoid invalidating the register cache all the time. */ if (r->registers_initialized && (!riscv_rtos_enabled(target) || (previous_hartid == hartid)) - && target->reg_cache->reg_list[GDB_REGNO_XPR0].size == (long)riscv_xlen(target) + && target->reg_cache->reg_list[GDB_REGNO_XPR0].size == (unsigned)riscv_xlen(target) && (!riscv_rtos_enabled(target) || (r->rtos_hartid != -1))) { LOG_DEBUG("registers already initialized, skipping"); return; |