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authorTim Newsome <tim@sifive.com>2017-06-27 15:11:06 -0700
committerTim Newsome <tim@sifive.com>2017-06-27 15:11:06 -0700
commitb6f8efbf44e2488ef0eb9c6362a2d9e5a5f28f41 (patch)
tree84b3c1d7ee53a6f3429640413b7b39693ca91d23
parent4e2e730abef0789143a3e10db30eb2771e311731 (diff)
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Check for errors in read_csr().
Also slightly improve debugging output.
-rw-r--r--src/target/riscv/riscv-011.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c
index 79f10f1..bc7d459 100644
--- a/src/target/riscv/riscv-011.c
+++ b/src/target/riscv/riscv-011.c
@@ -764,10 +764,10 @@ static void cache_set32(struct target *target, unsigned int index, uint32_t data
if (info->dram_cache[index].valid &&
info->dram_cache[index].data == data) {
// This is already preset on the target.
- LOG_DEBUG("cache[0x%x] = 0x%x (hit)", index, data);
+ LOG_DEBUG("cache[0x%x] = 0x%08x: DASM(0x%x) (hit)", index, data, data);
return;
}
- LOG_DEBUG("cache[0x%x] = 0x%x", index, data);
+ LOG_DEBUG("cache[0x%x] = 0x%08x: DASM(0x%x)", index, data, data);
info->dram_cache[index].data = data;
info->dram_cache[index].valid = true;
info->dram_cache[index].dirty = true;
@@ -1033,6 +1033,7 @@ static int wait_for_state(struct target *target, enum target_state state)
static int read_csr(struct target *target, uint64_t *value, uint32_t csr)
{
+ riscv011_info_t *info = get_info(target);
cache_set32(target, 0, csrr(S0, csr));
cache_set_store(target, 1, S0, SLOT0);
cache_set_jump(target, 2);
@@ -1042,6 +1043,13 @@ static int read_csr(struct target *target, uint64_t *value, uint32_t csr)
*value = cache_get(target, SLOT0);
LOG_DEBUG("csr 0x%x = 0x%" PRIx64, csr, *value);
+ uint32_t exception = cache_get32(target, info->dramsize-1);
+ if (exception) {
+ LOG_ERROR("Got exception 0x%x when reading CSR 0x%x", exception, csr);
+ *value = ~0;
+ return ERROR_FAIL;
+ }
+
return ERROR_OK;
}