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| author | Dmitry Ryzhov <dmitry.ryzhov@cloudbear.ru> | 2017-06-30 19:15:58 +0300 |
|---|---|---|
| committer | Dmitry Ryzhov <dmitry.ryzhov@cloudbear.ru> | 2017-06-30 19:15:58 +0300 |
| commit | 7d451e00f5c94a8f72f5abfd80a467e0e6a39bc6 (patch) | |
| tree | b5adf04b71e266a5993a95d50b82384681b84af0 | |
| parent | 4e2e730abef0789143a3e10db30eb2771e311731 (diff) | |
| download | riscv-openocd-7d451e00f5c94a8f72f5abfd80a467e0e6a39bc6.zip riscv-openocd-7d451e00f5c94a8f72f5abfd80a467e0e6a39bc6.tar.gz riscv-openocd-7d451e00f5c94a8f72f5abfd80a467e0e6a39bc6.tar.bz2 | |
Restore value of temporary register (s0) in examine OpenOCD procedure in case of core can not execute 64 bit instruction.
| -rw-r--r-- | src/target/riscv/riscv-013.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 60846de..f45ba4f 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1175,6 +1175,12 @@ static int examine(struct target *target) * In order to make this work we first need to */ int offset = (progbuf_addr % 8 == 0) ? -4 : 0; + /* This program uses a temporary register. If the core can not + * execute 64 bit instruction, the original value of temporary + * register will not be restored due to an exception. So we have to + * restore it manually in that case. */ + uint64_t s0 = riscv_get_register(target, GDB_REGNO_S0); + struct riscv_program program64; riscv_program_init(&program64, target); riscv_program_csrrw(&program64, GDB_REGNO_S0, GDB_REGNO_S0, GDB_REGNO_DSCRATCH); @@ -1190,6 +1196,8 @@ static int examine(struct target *target) + dmi_read(target, DMI_PROGBUF0 + (4 + offset) / 4) - 4; r->xlen[i] = 64; + } else { + riscv_set_register(target, GDB_REGNO_S0, s0); } /* Display this as early as possible to help people who are using |