riscv-opcodes.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2021-06-07	Add wfmi instructionwfmi	Andrew Waterman	1	-1/+1

2021-06-04	scalar-crypto: Opcode updates for v0.9.2 (#66)	Ben Marshall	1	-1/+1
	- Change AES32* and SM4* instructions back to regular R-type encoding. On branch scalar-crypto-v0.9.2 Changes to be committed: modified: opcodes-rv32k modified: opcodes-rv64k modified: opcodes-rvk modified: parse_opcodes
2021-04-05	Add fence.tso and pause instructions	Andrew Waterman	1	-2/+2

2021-03-08	Merge pull request #63 from ben-marshall/scalar-crypto	Andrew Waterman	1	-2/+70
	scalar-crypto: Add opcodes for RV32K, RV64K
2021-02-23	rvv: add vsetivli	Chih-Min Chao	1	-0/+1
	Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-02-19	scalar-crypto: Apply suggestions from code review	Ben Marshall	1	-1/+0
	Co-authored-by: Megan Wachs <megan@sifive.com>
2021-02-19	scalar-crypto: Add opcodes for RV32K, RV64K	Ben Marshall	1	-2/+71
	- Adds opcodes for RV32 and RV64 scalar crypto. - opcodes-rvk contains encodings which are for RV32 and RV64 base ISAs - opcodes-rv32/64k contains encodings which are for RV32 or RV64 - parse_opcodes has been modified: - Wnable instructions to be listed as either RV32 or RV64 only, allowing these opcodes to overlap. - The C backend has been modifed to emit the "DECLARE_RV32_ONLY" or "DECLARE_RV64_ONLY" macros as needed. - The other backends have not been modified, and may need to be in the future. On branch scalar-crypto Changes to be committed: modified: Makefile new file: opcodes-rv32k new file: opcodes-rv64k new file: opcodes-rvk modified: parse_opcodes
2021-01-22	Update Go instruction encoding generation (#34)	Joel Sing	1	-4/+4
	Remove the 'ok' value since this is redundant - an invalid instruction can already be identified by a nil return value. Also, include the script flags in the 'DO NOT EDIT' header.
2020-11-08	Support generating Rust code (#52)	Ngo Iok Ui (Wu Yu Wei)	1	-0/+13

2020-10-14	Adding four trigger CSRs to the list (#50)	Jan Matyas	1	-0/+4
	Adding these four CSRs to parse_opcodes: - 0x7a4 tinfo - 0x7a5 tcontrol - 0x7a8 mcontext - 0x7aa scontext
2020-07-31	hyperviosr: add csr mask and interrupt macro name	Chih-Min Chao	1	-1/+5
	This part copy the implementation which has been merged in spike Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-14	rvv: add new vcsr for vector spec 0.9 (#42)	Chih-Min Chao	1	-0/+1
	Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-31	update csr to draft-20200326-af69f79 (#39)	Chih-Min Chao	1	-1/+16
	about two parts 1. hypervisor related 2. missing high part for rv32 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-29	Using OrderedDict to keep encodings for match/mask. (#38)	Kito Cheng	1	-2/+3
	- Prevent got different result in different python env.
2020-02-28	Add mcountinhibit CSR	Andrew Waterman	1	-0/+1

2020-02-24	Add N-extension CSRs and status bits. (#37)	michael-roe	1	-0/+2

2019-11-28	rvv: add vleb csr register and mstatus.vs field	Chih-Min Chao	1	-0/+1
	1. vleb is read-only CSR to keep vector implementation lenght in byte 2. mstatus.vs is similar to mstatus.fs and designed to keep vector extension state Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-08-03	Fix crash introduced by #30	Andrew Waterman	1	-1/+1

2019-08-03	(Partially) fix #30 (#31)	Tommy Thorn	1	-0/+1089
	* (Partially) fix #30 With this change (and a renamed parse-opcodes) it's possible to as a Python module without having to patch the repo. Example: from parse_opcodes import parse_inputs if __name__ == "__main__": (namelist, pseudos, mask, match, arguments) = parse_inputs(["opcodes", "opcodes-rvc"]) * Fix #30: Rename parse-opcode to parse_opcode to enable module use