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riscv-opcodes.git
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incoresemi-migration-to-new-format
latex-based-output-refactor
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2023-11-24
SSP CSR introduced by Zicfiss
Ved Shanbhogue
1
-0
/
+1
2023-11-24
CSR fields introduced by Zicfiss
Ved Shanbhogue
1
-0
/
+3
2023-11-01
Merge pull request #206 from ved-rivos/zabha
Andrew Waterman
1
-0
/
+23
2023-10-29
Add Zabha AMO inst code points
Ved Shanbhogue
1
-0
/
+23
2023-10-26
Merge pull request #205 from tomhepworth/master
Andrew Waterman
1
-1
/
+3
2023-10-26
Clarified syntax of regular instructions
Thomas Hepworth
1
-1
/
+3
2023-10-20
Merge pull request #201 from mehnadnerd/master
Andrew Waterman
1
-0
/
+8
2023-10-19
Making explicit that the aq bit is set for load-acquire, rl bit is set for st...
brs
1
-8
/
+8
2023-10-18
Changing it so Zalasr has one bit hardcoded for each, to reduce opcode confus...
brs
1
-8
/
+8
2023-10-18
Adding load-acquire/store-release. Note they are written here as `lb.` for th...
brs
1
-0
/
+8
2023-10-17
Add pseudo-instructions for Zimop/Zcmop (#194)
Ved Shanbhogue
3
-51
/
+114
2023-10-17
Merge pull request #202 from a4lg/remove-zvamo
Andrew Waterman
1
-41
/
+0
2023-10-16
Remove unratified 'Zvamo' instructions from rv_v
Tsukasa OI
1
-41
/
+0
2023-10-09
Merge pull request #200 from felixhauptmann/master
Andrew Waterman
2
-131
/
+131
2023-10-10
fix csv parsing
Felix Hauptmann
2
-131
/
+131
2023-09-28
Merge pull request #198 from sequencer/sdext
Neel Gala
1
-0
/
+0
2023-09-28
rename rv_debug to rv_sdext
Jiuyang Liu
1
-0
/
+0
2023-09-27
Merge pull request #197 from sequencer/split_debug
Andrew Waterman
2
-1
/
+2
2023-09-27
split dret from rv_system to rv_debug
Jiuyang Liu
2
-1
/
+2
2023-09-26
Merge pull request #195 from sequencer/constant_csv
Andrew Waterman
5
-611
/
+590
2023-09-25
split arg_lut, causes, csr, csr32 from constants.py
Jiuyang Liu
5
-611
/
+590
2023-09-24
Merge pull request #196 from sequencer/patch-1
Andrew Waterman
1
-1
/
+0
2023-09-25
Remove duplicate zimm
Jiuyang Liu
1
-1
/
+0
2023-09-23
Merge pull request #193 from riscv/fix-changes-in-189
Neel Gala
1
-0
/
+3
2023-09-20
retain the original shift instructions as pseudo-ops as well
Neel Gala
1
-0
/
+3
2023-09-19
Merge pull request #192 from sequencer/fix_dup
Andrew Waterman
1
-5
/
+5
2023-09-20
fix instruction duplication between rv128_c and rv64_c
Jiuyang Liu
1
-5
/
+5
2023-09-16
Merge pull request #189 from charlie-rivos/support_rv32_shift
Andrew Waterman
1
-3
/
+3
2023-09-16
Merge pull request #188 from charlie-rivos/fix_c_addiw
Andrew Waterman
2
-7
/
+4
2023-09-15
Generate compressed shift instructions for rv32
Charlie Jenkins
1
-3
/
+3
2023-09-15
C.ADDIW cannot have an rd of 0
Charlie Jenkins
2
-7
/
+4
2023-09-15
Merge pull request #187 from ved-rivos/zimop
Andrew Waterman
2
-0
/
+62
2023-09-15
add unratified Zcmop instructions
Ved Shanbhogue
1
-0
/
+13
2023-09-15
add unratified Zimop instructions
Ved Shanbhogue
1
-0
/
+49
2023-08-13
Merge pull request #186 from ved-rivos/svadu1
Andrew Waterman
1
-4
/
+4
2023-08-13
Svadu: Rename HADE to ADUE
Ved Shanbhogue
1
-4
/
+4
2023-07-31
rv64_q_zfa: rs2 is variable field.
Nikola Rajovic
1
-1
/
+1
2023-07-31
rv32_d_zfa: rs2 is variable field.
Nikola Rajovic
1
-1
/
+1
2023-07-25
Merge pull request #181 from rivosinc/add_smcntrpmf_csrs
Andrew Waterman
1
-0
/
+4
2023-07-25
Merge pull request #182 from nrajovic/fix_vector_mask_register_logical_instru...
Andrew Waterman
1
-8
/
+8
2023-07-25
rv_v: fix for Vector Mask-Register Logical instructions.
Nikola Rajovic
1
-8
/
+8
2023-07-24
Add Smcntrpmf CSRs
Atul Khare
1
-0
/
+4
2023-07-12
Merge branch 'rivosinc-smdeleg_definitions'
Andrew Waterman
2
-0
/
+14
2023-07-12
Add Smcdeleg CSR+constants
Atul Khare
2
-0
/
+14
2023-07-10
Merge pull request #178 from rivosinc/smcsrind_sscsrind_csrs
Andrew Waterman
1
-0
/
+15
2023-07-10
Add Smcsrind/Sscsrind CSRs
Atul Khare
1
-0
/
+15
2023-05-26
Merge pull request #177 from liweiwei90/plct-bf16-dev
Neel Gala
1
-2
/
+2
2023-05-19
Update encodings for vfwmaccbf16.vv/vf
Weiwei Li
1
-2
/
+2
2023-05-15
Merge pull request #176 from ved-rivos/zacas
Neel Gala
2
-0
/
+3
2023-05-13
add amocas.q (RV64 only) zacas instruction
Ved Shanbhogue
1
-0
/
+1
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