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\chapter{Preface}
This is version \specrev\ of the document describing the RISC-V
user-level architecture. The document contains the following
versions of the RISC-V ISA modules:
\begin{table}[hbt]
\centering
\begin{tabular}{|c|l|c|}
\hline
Base & Version & Frozen? \\
\hline
RV32I & 2.0 & Y \\
RV32E & 1.9 & N \\
RV64I & 2.0 & Y \\
RV128I & 1.7 & N \\
\hline
Extension & Version & Frozen? \\
\hline
M & 2.0 & Y \\
A & 2.0 & Y \\
F & 2.0 & Y \\
D & 2.0 & Y \\
Q & 2.0 & Y \\
L & 0.0 & N \\
C & 1.9 & N \\
V & 0.1 & N \\
B & 0.0 & N \\
J & 0.0 & N \\
T & 0.0 & N \\
P & 0.1 & N \\
\hline
\end{tabular}
\end{table}
To date, no parts of the standard have been officially ratified by the
RISC-V Foundation, but the components labeled ``frozen'' above are not
expected to change during the ratification process.
The major changes in this version of the document include:
\begin{itemize}
\parskip 0pt
\itemsep 1pt
\item The previous version of this document was released under a
Creative Commons Attribution 4.0 International Licence by the
original authors, and this and future versions of this document will
be released under the same licence.
\item Improvements to the description and commentary.
\item Modified implicit hinting suggestion on JALR to support more efficient
macro-op fusion of LUI/JALR and AUIPC/JALR pairs.
\item Clarification of constraints on load-reserved/store-conditional sequences.
\item Clarified purpose and behavior of high-order bits of {\tt fcsr}.
\item Corrected the description of the FNMADD.{\em fmt} and FNMSUB.{\em fmt}
instructions, which had suggested the incorrect sign of a zero result.
\item Instructions FMV.S.X and FMV.X.S were renamed to FMV.W.X and
FMV.X.W respectively to be more consistent with their
semantics, which did not change.
The old names will continue to be supported in the tools.
\item Specified behavior of narrower ($<$FLEN) floating-point values held in
wider {\tt f} registers using NaN-boxing model.
\item Defined the exception behavior of FMA($\infty$, 0, qNaN).
\item A draft proposal of the V vector instruction set extension.
\item An expanded pseudoinstruction listing.
\item A new table of control and status register (CSR) mappings.
\item Removal of the calling convention chapter, which has been superseded by
the RISC-V ELF psABI Specification~\cite{riscv-elf-psabi}.
\end{itemize}
\section*{Preface to Document Version 2.1}
This is version 2.1 of the document describing the RISC-V user-level
architecture. Note the frozen user-level ISA base and extensions
IMAFDQ version 2.0 have not changed from the previous version of this
document~\cite{riscvtr2}, but some specification holes have been fixed
and the documentation has been improved. Some changes have been made
to the software conventions.
\begin{itemize}
\parskip 0pt
\itemsep 1pt
\item Numerous additions and improvements to the commentary sections.
\item Separate version numbers for each chapter.
\item Modification to long instruction encodings $>$64 bits to avoid
moving the {\em rd} specifier in very long instruction formats.
\item CSR instructions are now described in the base integer format
where the counter registers are introduced, as opposed to only being
introduced later in the floating-point section (and the companion
privileged architecture manual).
\item The SCALL and SBREAK instructions have been renamed to ECALL and
EBREAK, respectively. Their encoding and functionality are unchanged.
\item Clarification of floating-point NaN handling, and a new canonical NaN
value.
\item Clarification of values returned by floating-point to integer
conversions that overflow.
\item Clarification of LR/SC allowed successes and required failures,
including use of compressed instructions in the sequence.
\item A new RV32E base ISA proposal for reduced integer register
counts, supports MAC extensions.
\item A revised calling convention.
\item Relaxed stack alignment for soft-float calling convention, and
description of the RV32E calling convention.
\item A revised proposal for the C compressed extension, version 1.9.
\end{itemize}
\section*{Preface to Version 2.0}
This is the second release of the user ISA specification, and we
intend the specification of the base user ISA plus general extensions
(i.e., IMAFD) to remain fixed for future development. The following
changes have been made since Version 1.0~\cite{riscvtr} of this ISA
specification.
\vspace{-0.1in}
\begin{itemize}
\parskip 0pt
\itemsep 1pt
\item The ISA has been divided into an integer base with several
standard extensions.
\item The instruction formats have been rearranged to make immediate
encoding more efficient.
\item The base ISA has been defined to have a little-endian memory system, with
big-endian or bi-endian as non-standard variants.
\item Load-Reserved/Store-Conditional (LR/SC) instructions have been added in
the atomic instruction extension.
\item AMOs and LR/SC can support the release consistency model.
\item The FENCE instruction provides finer-grain memory and I/O
orderings.
\item An AMO for fetch-and-XOR (AMOXOR) has been added, and the
encoding for AMOSWAP has been changed to make room.
\item The AUIPC instruction, which adds a 20-bit upper immediate to
the PC, replaces the RDNPC instruction, which only read the current
PC value. This results in significant savings for position-independent
code.
\item The JAL instruction has now moved to the U-Type format with an
explicit destination register, and the J instruction has been
dropped being replaced by JAL with {\em rd}={\tt x0}. This removes
the only instruction with an implicit destination register and
removes the J-Type instruction format from the base ISA. There is
an accompanying reduction in JAL reach, but a significant reduction
in base ISA complexity.
\item The static hints on the JALR instruction have been dropped. The
hints are redundant with the {\em rd} and {\em rs1} register
specifiers for code compliant with the standard calling convention.
\item The JALR instruction now clears the lowest bit of the calculated
target address, to simplify hardware and to allow auxiliary information
to be stored in function pointers.
\item The MFTX.S and MFTX.D instructions have been renamed to FMV.X.S and
FMV.X.D, respectively. Similarly, MXTF.S and MXTF.D instructions have been
renamed to FMV.S.X and FMV.D.X, respectively.
\item The MFFSR and MTFSR instructions have been renamed to FRCSR and FSCSR,
respectively. FRRM, FSRM, FRFLAGS, and FSFLAGS instructions have been added
to individually access the rounding mode and exception flags subfields of
the {\tt fcsr}.
\item The FMV.X.S and FMV.X.D instructions now source their operands
from {\em rs1}, instead of {\em rs2}. This change simplifies datapath
design.
\item FCLASS.S and FCLASS.D floating-point classify instructions have been
added.
\item A simpler NaN generation and propagation scheme has been
adopted.
\item For RV32I, the system performance counters have been extended to
64-bits wide, with separate read access to the upper and lower 32 bits.
\item Canonical NOP and MV encodings have been defined.
\item Standard instruction-length encodings have been defined for 48-bit,
64-bit, and $>$64-bit instructions.
\item Description of a 128-bit address space variant, RV128, has been added.
\item Major opcodes in the 32-bit base instruction format have been
allocated for user-defined custom extensions.
\item A typographical error that suggested that stores source their
data from {\em rd} has been corrected to refer to {\em rs2}.
\end{itemize}
\vspace{-0.1in}
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