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\chapter{Control and Status Register (CSR) Instructions}
\label{csrinsts}
RISC-V defines a separate address space of 4096 Control and Status
registers associated with each hart. This chapter defines the full
set of CSR instructions that operate on these CSRs.
\begin{commentary}
While CSRs are primarily used by the privileged architecture, there
are several uses in unprivileged code including for counters and
timers, and for floating-point status.
The counters and timers are no longer considered mandatory parts of
the standard base ISAs, and so the CSR instructions required to
access them have been moved out of the base ISA chapter into this
separate chapter.
\end{commentary}
\section{CSR Instructions}
All CSR instructions atomically read-modify-write a single CSR, whose
CSR specifier is encoded in the 12-bit {\em csr} field of the
instruction held in bits 31--20. The immediate forms use a 5-bit
zero-extended immediate encoded in the {\em rs1} field.
\vspace{-0.2in}
\begin{center}
\begin{tabular}{M@{}R@{}F@{}R@{}S}
\\
\instbitrange{31}{20} &
\instbitrange{19}{15} &
\instbitrange{14}{12} &
\instbitrange{11}{7} &
\instbitrange{6}{0} \\
\hline
\multicolumn{1}{|c|}{csr} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{funct3} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{opcode} \\
\hline
12 & 5 & 3 & 5 & 7 \\
source/dest & source & CSRRW & dest & SYSTEM \\
source/dest & source & CSRRS & dest & SYSTEM \\
source/dest & source & CSRRC & dest & SYSTEM \\
source/dest & uimm[4:0] & CSRRWI & dest & SYSTEM \\
source/dest & uimm[4:0] & CSRRSI & dest & SYSTEM \\
source/dest & uimm[4:0] & CSRRCI & dest & SYSTEM \\
\end{tabular}
\end{center}
The CSRRW (Atomic Read/Write CSR) instruction atomically swaps values
in the CSRs and integer registers. CSRRW reads the old value of the
CSR, zero-extends the value to XLEN bits, then writes it to integer
register {\em rd}. The initial value in {\em rs1} is written to the
CSR. If {\em rd}={\tt x0}, then the instruction shall not read the CSR
and shall not cause any of the side-effects that might occur on a CSR
read.
The CSRRS (Atomic Read and Set Bits in CSR) instruction reads the
value of the CSR, zero-extends the value to XLEN bits, and writes it
to integer register {\em rd}. The initial value in integer register
{\em rs1} is treated as a bit mask that specifies bit positions to be
set in the CSR. Any bit that is high in {\em rs1} will cause the
corresponding bit to be set in the CSR, if that CSR bit is writable.
Other bits in the CSR are unaffected (though CSRs might have side
effects when written).
The CSRRC (Atomic Read and Clear Bits in CSR) instruction reads the
value of the CSR, zero-extends the value to XLEN bits, and writes it
to integer register {\em rd}. The initial value in integer register
{\em rs1} is treated as a bit mask that specifies bit positions to be
cleared in the CSR. Any bit that is high in {\em rs1} will cause the
corresponding bit to be cleared in the CSR, if that CSR bit is
writable. Other bits in the CSR are unaffected.
For both CSRRS and CSRRC, if {\em rs1}={\tt x0}, then the instruction
will not write to the CSR at all, and so shall not cause any of the
side effects that might otherwise occur on a CSR write, such as
raising illegal instruction exceptions on accesses to read-only CSRs.
Note that if {\em rs1} specifies a register holding a zero value other
than {\tt x0}, the instruction will still attempt to write the
unmodified value back to the CSR and will cause any attendant side effects.
The CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS,
and CSRRC respectively, except they update the CSR using an XLEN-bit
value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field
encoded in the {\em rs1} field instead of a value from an integer
register. For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then
these instructions will not write to the CSR, and shall not cause any
of the side effects that might otherwise occur on a CSR write. For
CSRRWI, if {\em rd}={\tt x0}, then the instruction shall not read the
CSR and shall not cause any of the side-effects that might occur on a
CSR read.
Some CSRs, such as the instructions retired counter, {\tt instret}, may be
modified as side effects of instruction execution. In these cases, if a CSR
access instruction reads a CSR, it reads the value prior to the execution of
the instruction. If a CSR access instruction writes a CSR, the update occurs
after the execution of the instruction. In particular, a value written to
{\tt instret} by one instruction will be the value read by the following
instruction (i.e., the increment of {\tt instret} caused by the first
instruction retiring happens before the write of the new value).
The assembler pseudoinstruction to read a CSR, CSRR {\em rd, csr}, is
encoded as CSRRS {\em rd, csr, x0}. The assembler pseudoinstruction
to write a CSR, CSRW {\em csr, rs1}, is encoded as CSRRW {\em x0, csr,
rs1}, while CSRWI {\em csr, uimm}, is encoded as CSRRWI {\em x0,
csr, uimm}.
Further assembler pseudoinstructions are defined to set and clear
bits in the CSR when the old value is not required: CSRS/CSRC {\em
csr, rs1}; CSRSI/CSRCI {\em csr, uimm}.
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